[PATCH] D32247: Switch AArch64 to use reduction intrinsics
Amara Emerson via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Wed Apr 26 03:31:33 PDT 2017
aemerson added a comment.
No changes are needed on the MC side. The same target-specific reduction DAG nodes (e.g. AArch64ISD::UADDV) should be created and from then on everything should work as before.
================
Comment at: lib/Target/AArch64/AArch64TargetTransformInfo.cpp:690
+ case Instruction::Add:
+ return Ty->getScalarSizeInBits() * Ty->getVectorNumElements() >= 128;
+ default:
----------------
rengolin wrote:
> For now, shouldn't this be `== 128`?
It's needed because vectors can be oversize, e.g. v8i32. We still want to use reductions for that as legalisation will split the vector later.
================
Comment at: lib/Target/AArch64/AArch64TargetTransformInfo.cpp:697
+
+bool AArch64TTIImpl::useMinMaxReductionIntrinsic(Type *Ty, bool IsMaxOp,
+ bool IsSigned,
----------------
FYI, I haven't yet updated this version of the patch, the current generic reduction patch combines the two hooks into one so this function will merge into the one above when I do.
Repository:
rL LLVM
https://reviews.llvm.org/D32247
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