[llvm] r301106 - [ARM] ScheduleDAGRRList::DelayForLiveRegsBottomUp must consider OptionalDefs

[Artyom Skrobov via llvm-commits]

Author: askrobov
Date: Sun Apr 23 01:58:08 2017
New Revision: 301106

URL: http://llvm.org/viewvc/llvm-project?rev=301106&view=rev
Log:
[ARM] ScheduleDAGRRList::DelayForLiveRegsBottomUp must consider OptionalDefs

Summary:
D30400 has enabled tADC and tSBC instructions to be unglued, thereby allowing CPSR to remain live between Thumb1 scheduling units.

Most Thumb1 instructions have an OptionalDef for CPSR; but the scheduler ignored the OptionalDefs, and could unwittingly insert a flag-setting instruction in between an ADDS and the corresponding ADC.

Reviewers: javed.absar, atrick, MatzeB, t.p.northover, jmolloy, rengolin

Reviewed By: javed.absar

Subscribers: rogfer01, efriedma, aemerson, rengolin, llvm-commits, MatzeB

Differential Revision: https://reviews.llvm.org/D31081

Added:
    llvm/trunk/test/CodeGen/Thumb/optionaldef-scheduling.ll
Modified:
    llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp?rev=301106&r1=301105&r2=301106&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp Sun Apr 23 01:58:08 2017
@@ -1320,6 +1320,18 @@ DelayForLiveRegsBottomUp(SUnit *SU, Smal
                                RegAdded, LRegs);
 
     const MCInstrDesc &MCID = TII->get(Node->getMachineOpcode());
+    if (MCID.hasOptionalDef()) {
+      // Most ARM instructions have an OptionalDef for CPSR, to model the S-bit.
+      // This operand can be either a def of CPSR, if the S bit is set; or a use
+      // of %noreg.  When the OptionalDef is set to a valid register, we need to
+      // handle it in the same way as an ImplicitDef.
+      for (unsigned i = 0; i < MCID.getNumDefs(); ++i)
+        if (MCID.OpInfo[i].isOptionalDef()) {
+          const SDValue &OptionalDef = Node->getOperand(i - Node->getNumValues());
+          unsigned Reg = cast<RegisterSDNode>(OptionalDef)->getReg();
+          CheckForLiveRegDef(SU, Reg, LiveRegDefs.get(), RegAdded, LRegs, TRI);
+        }
+    }
     if (!MCID.ImplicitDefs)
       continue;
     for (const MCPhysReg *Reg = MCID.getImplicitDefs(); *Reg; ++Reg)

Added: llvm/trunk/test/CodeGen/Thumb/optionaldef-scheduling.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb/optionaldef-scheduling.ll?rev=301106&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/Thumb/optionaldef-scheduling.ll (added)
+++ llvm/trunk/test/CodeGen/Thumb/optionaldef-scheduling.ll Sun Apr 23 01:58:08 2017
@@ -0,0 +1,18 @@
+; RUN: llc -mtriple=thumb-eabi %s -verify-machineinstrs -o - | FileCheck %s
+; RUN: llc -mtriple=thumbv6-eabi %s -verify-machineinstrs -o - | FileCheck %s
+
+define i1 @test(i64 %arg) {
+entry:
+  %ispos = icmp sgt i64 %arg, -1
+  %neg = sub i64 0, %arg
+  %sel = select i1 %ispos, i64 %arg, i64 %neg
+  %cmp2 = icmp eq i64 %sel, %arg
+  ret i1 %cmp2
+}
+
+; The scheduler used to ignore OptionalDefs, and could unwittingly insert
+; a flag-setting instruction in between an ADDS and the corresponding ADC.
+
+; CHECK: adds
+; CHECK-NOT: eors
+; CHECK: adcs