[PATCH] D24623: [AMDGPU] Implement memory model

[Tony Tye via Phabricator via llvm-commits]

t-tye added inline comments.


================
Comment at: lib/Target/AMDGPU/SIMemoryLegalizer.cpp:347
+  case AMDGPUSynchronizationScope::Agent: {
+    Changed |= SetGLC(MI);
+
----------------
Should this be done? For rmw the glc bit controls whether the original value is returned, not whether the L1 cache is bypassed.


================
Comment at: lib/Target/AMDGPU/SIMemoryLegalizer.cpp:397
+  case AMDGPUSynchronizationScope::Agent: {
+    Changed |= SetGLC(MI);
+
----------------
Ditto.


================
Comment at: lib/Target/AMDGPU/SIMemoryLegalizer.cpp:419
+  case AMDGPUSynchronizationScope::SignalHandler: {
+    Changed |= SetGLC(MI);
+    break;
----------------
Ditto.


https://reviews.llvm.org/D24623