[llvm] r300319 - [AMDGPU][MC] Corrected ds_write_src2_* to require one offset instead of two.
Dmitry Preobrazhensky via llvm-commits
llvm-commits at lists.llvm.org
Fri Apr 14 05:28:09 PDT 2017
Author: dpreobra
Date: Fri Apr 14 07:28:07 2017
New Revision: 300319
URL: http://llvm.org/viewvc/llvm-project?rev=300319&view=rev
Log:
[AMDGPU][MC] Corrected ds_write_src2_* to require one offset instead of two.
Fixed bug 32551: https://bugs.llvm.org//show_bug.cgi?id=32551
Reviewers: vpykhtin
Differential Revision: https://reviews.llvm.org/D31809
Modified:
llvm/trunk/lib/Target/AMDGPU/DSInstructions.td
llvm/trunk/test/MC/AMDGPU/ds.s
Modified: llvm/trunk/lib/Target/AMDGPU/DSInstructions.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/DSInstructions.td?rev=300319&r1=300318&r2=300319&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/DSInstructions.td (original)
+++ llvm/trunk/lib/Target/AMDGPU/DSInstructions.td Fri Apr 14 07:28:07 2017
@@ -88,18 +88,6 @@ class DS_1A1D_NORET<string opName, Regis
let has_vdst = 0;
}
-class DS_1A_Off8_NORET<string opName> : DS_Pseudo<opName,
- (outs),
- (ins VGPR_32:$addr, offset0:$offset0, offset1:$offset1, gds:$gds),
- "$addr $offset0$offset1$gds"> {
-
- let has_data0 = 0;
- let has_data1 = 0;
- let has_vdst = 0;
- let has_offset = 0;
- let AsmMatchConverter = "cvtDSOffset01";
-}
-
class DS_1A2D_NORET<string opName, RegisterClass rc = VGPR_32>
: DS_Pseudo<opName,
(outs),
@@ -450,8 +438,8 @@ def DS_XOR_SRC2_B64 : DS_1A<"ds_xor_sr
def DS_MIN_SRC2_F64 : DS_1A<"ds_min_src2_f64">;
def DS_MAX_SRC2_F64 : DS_1A<"ds_max_src2_f64">;
-def DS_WRITE_SRC2_B32 : DS_1A_Off8_NORET<"ds_write_src2_b32">;
-def DS_WRITE_SRC2_B64 : DS_1A_Off8_NORET<"ds_write_src2_b64">;
+def DS_WRITE_SRC2_B32 : DS_1A<"ds_write_src2_b32">;
+def DS_WRITE_SRC2_B64 : DS_1A<"ds_write_src2_b64">;
let Uses = [EXEC], mayLoad = 0, mayStore = 0, isConvergent = 1 in {
def DS_SWIZZLE_B32 : DS_1A_RET <"ds_swizzle_b32">;
Modified: llvm/trunk/test/MC/AMDGPU/ds.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AMDGPU/ds.s?rev=300319&r1=300318&r2=300319&view=diff
==============================================================================
--- llvm/trunk/test/MC/AMDGPU/ds.s (original)
+++ llvm/trunk/test/MC/AMDGPU/ds.s Fri Apr 14 07:28:07 2017
@@ -19,13 +19,13 @@ ds_add_u32 v2, v4 offset:16
// Checks for 2 8-bit Offsets
//===----------------------------------------------------------------------===//
-ds_write_src2_b32 v2 offset0:4 offset1:8
-// SICI: ds_write_src2_b32 v2 offset0:4 offset1:8 ; encoding: [0x04,0x08,0x34,0xda,0x02,0x00,0x00,0x00]
-// VI: ds_write_src2_b32 v2 offset0:4 offset1:8 ; encoding: [0x04,0x08,0x1a,0xd9,0x02,0x00,0x00,0x00]
+ds_write_src2_b32 v2 offset:2052
+// SICI: ds_write_src2_b32 v2 offset:2052 ; encoding: [0x04,0x08,0x34,0xda,0x02,0x00,0x00,0x00]
+// VI: ds_write_src2_b32 v2 offset:2052 ; encoding: [0x04,0x08,0x1a,0xd9,0x02,0x00,0x00,0x00]
-ds_write_src2_b64 v2 offset0:4 offset1:8
-// SICI: ds_write_src2_b64 v2 offset0:4 offset1:8 ; encoding: [0x04,0x08,0x34,0xdb,0x02,0x00,0x00,0x00]
-// VI: ds_write_src2_b64 v2 offset0:4 offset1:8 ; encoding: [0x04,0x08,0x9a,0xd9,0x02,0x00,0x00,0x00]
+ds_write_src2_b64 v2 offset:2052
+// SICI: ds_write_src2_b64 v2 offset:2052 ; encoding: [0x04,0x08,0x34,0xdb,0x02,0x00,0x00,0x00]
+// VI: ds_write_src2_b64 v2 offset:2052 ; encoding: [0x04,0x08,0x9a,0xd9,0x02,0x00,0x00,0x00]
ds_write2_b32 v2, v4, v6 offset0:4
// SICI: ds_write2_b32 v2, v4, v6 offset0:4 ; encoding: [0x04,0x00,0x38,0xd8,0x02,0x04,0x06,0x00]
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