[PATCH] D32028: [AArch64] Avoid partial register writes on lane 0 of BUILD_VECTOR for i8/i16/f16

Ahmed Bougacha via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Thu Apr 13 16:20:26 PDT 2017

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ab accepted this revision.
ab added a comment.
This revision is now accepted and ready to land.

Nice, LGTM


https://reviews.llvm.org/D32028

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