[PATCH] D32028: [AArch64] Avoid partial register writes on lane 0 of BUILD_VECTOR for i8/i16/f16

[Adam Nemet via Phabricator via llvm-commits]

anemet created this revision.
Herald added subscribers: rengolin, aemerson.
Herald added a reviewer: javed.absar.

This further improves Ahmed's change in https://reviews.llvm.org/rL299482.  See the new comment for the
rationale.

The patch recovers most of the regression for bzip2 after https://reviews.llvm.org/D31965. We're down
to +2.68% from +6.97%.


https://reviews.llvm.org/D32028

Files:
  lib/Target/AArch64/AArch64ISelLowering.cpp
  test/CodeGen/AArch64/arm64-indexed-vector-ldst.ll
  test/CodeGen/AArch64/arm64-neon-copy.ll
  test/CodeGen/AArch64/concat_vector-scalar-combine.ll

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