[PATCH] D31872: AMDGPU: Minor SReg64 register class refactoring

[Matt Arsenault via Phabricator via llvm-commits]

arsenm added a comment.

In https://reviews.llvm.org/D31872#723085, @kzhuravl wrote:

> In https://reviews.llvm.org/D31872#722575, @arsenm wrote:
>
> > I think this requires changing the register class for SSrc_32/VSrc_32 to be the one that includes the special 32-bit regs. I think I started doing this to start supporting vccz and the other special 1-bit inputs
>
>
> I do not think so. src_*_base and src_*_limit are 64 bit inline constants. Here is an example of src_shared_base:
>
>   {SMB.shared_base[15:0], 48’h000000000000}
>
>
> src_*_base and src_*_limit also do not have subregisters.


According to the manual it says if used with a 32-bit input, the 32 LSBs are used, so I guess it has sub0 but not sub1


https://reviews.llvm.org/D31872