[PATCH] D31817: [ARM/AArch64] Ensure valid vector element types for interleaved accesses

[Chad Rosier via Phabricator via llvm-commits]

mcrosier accepted this revision.
mcrosier added a comment.
This revision is now accepted and ready to land.

Looks straight forward.



================
Comment at: lib/Target/AArch64/AArch64ISelLowering.cpp:7264
+  // 128 will be split into multiple interleaved accesses.
+  if (VecSize != 64 && VecSize % 128 != 0)
+    return false;
----------------
  return VecSize == 64 || VecSize % 128 == 0;


================
Comment at: lib/Target/ARM/ARMISelLowering.cpp:13624
+  // 128 will be split into multiple interleaved accesses.
+  if (VecSize != 64 && VecSize % 128 != 0)
+    return false;
----------------
  return VecSize == 64 || VecSize % 128 == 0;


https://reviews.llvm.org/D31817