[PATCH] D31651: Fix in SelectionDAG::getNode() to not produce illegal BUILD_VECTOR operands

[Jonas Paulsson via Phabricator via llvm-commits]

jonpa updated this revision to Diff 94022.
jonpa added a comment.

Test case (which I did not manage to reduce further...)


https://reviews.llvm.org/D31651

Files:
  lib/CodeGen/SelectionDAG/SelectionDAG.cpp
  test/CodeGen/SystemZ/DAGCombiner_illegal_BUILD_VECTOR.ll


Index: test/CodeGen/SystemZ/DAGCombiner_illegal_BUILD_VECTOR.ll
===================================================================
--- /dev/null
+++ test/CodeGen/SystemZ/DAGCombiner_illegal_BUILD_VECTOR.ll
@@ -0,0 +1,26 @@
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s
+;
+; Check that DAGCombiner does not crash after producing an illegal
+; BUILD_VECTOR node.
+
+
+define void @pr32422() {
+; CHECK:        cdbr    %f0, %f0
+; CHECK:        jo      .LBB0_1
+
+BB:
+  %I = insertelement <8 x i8> zeroinitializer, i8 -95, i32 3
+  %I8 = insertelement <8 x i8> zeroinitializer, i8 -119, i32 2
+  %FC = uitofp <8 x i8> %I8 to <8 x float>
+  %Cmp18 = fcmp uno <8 x float> zeroinitializer, %FC
+  %I22 = insertelement <8 x i1> %Cmp18, i1 true, i32 5
+  br label %CF
+
+CF:                                               ; preds = %CF, %BB
+  %Cmp40 = fcmp uno double 0xC663C682E9619F00, undef
+  br i1 %Cmp40, label %CF, label %CF353
+
+CF353:                                            ; preds = %CF
+  %E195 = extractelement <8 x i1> %I22, i32 4
+  ret void
+}
Index: lib/CodeGen/SelectionDAG/SelectionDAG.cpp
===================================================================
--- lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+++ lib/CodeGen/SelectionDAG/SelectionDAG.cpp
@@ -4126,35 +4126,36 @@
     assert(EVT.bitsLE(VT) && "Not extending!");
     if (EVT == VT) return N1;  // Not actually extending
 
-    auto SignExtendInReg = [&](APInt Val) {
+    auto SignExtendInReg = [&](APInt Val, llvm::EVT ScalarVT) {
       unsigned FromBits = EVT.getScalarSizeInBits();
       Val <<= Val.getBitWidth() - FromBits;
       Val = Val.ashr(Val.getBitWidth() - FromBits);
-      return getConstant(Val, DL, VT.getScalarType());
+      return getConstant(Val, DL, ScalarVT);
     };
 
     if (N1C) {
       const APInt &Val = N1C->getAPIntValue();
-      return SignExtendInReg(Val);
+      return SignExtendInReg(Val, VT.getScalarType());
     }
     if (ISD::isBuildVectorOfConstantSDNodes(N1.getNode())) {
+      // If the scalar type of VT is not legal, keep the original operand type.
+      llvm::EVT LegalScalarVT = (TLI->isTypeLegal(VT.getScalarType()) ?
+         VT.getScalarType() : N1.getOperand(0).getValueType().getScalarType());
+
       SmallVector<SDValue, 8> Ops;
       for (int i = 0, e = VT.getVectorNumElements(); i != e; ++i) {
         SDValue Op = N1.getOperand(i);
-        if (Op.isUndef()) {
-          Ops.push_back(getUNDEF(VT.getScalarType()));
-          continue;
-        }
-        if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
+        if (Op.isUndef())
+          Ops.push_back(getUNDEF(LegalScalarVT));
+        else {
+          ConstantSDNode *C = cast<ConstantSDNode>(Op);
           APInt Val = C->getAPIntValue();
-          Val = Val.zextOrTrunc(VT.getScalarSizeInBits());
-          Ops.push_back(SignExtendInReg(Val));
+          Val = Val.zextOrTrunc(LegalScalarVT.getSizeInBits());
+          Ops.push_back(SignExtendInReg(Val, LegalScalarVT));
           continue;
         }
-        break;
       }
-      if (Ops.size() == VT.getVectorNumElements())
-        return getBuildVector(VT, DL, Ops);
+      return getBuildVector(VT, DL, Ops);
     }
     break;
   }


-------------- next part --------------
A non-text attachment was scrubbed...
Name: D31651.94022.patch
Type: text/x-patch
Size: 3236 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20170404/44d322b7/attachment.bin>