[PATCH] D31651: Fix in SelectionDAG::getNode() to not produce BUILD_VECTOR operands
Jonas Paulsson via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Tue Apr 4 02:26:31 PDT 2017
jonpa created this revision.
Continued from: https://bugs.llvm.org//show_bug.cgi?id=32422
About the assert in LegalizeOp() that triggered:
llvm/llvm-dev/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:921: void {anonymous}::SelectionDAGLegalize::LegalizeOp(llvm::SDNode*): Assertion `(TLI.getTypeAction(*DAG.getContext(), Op.getValueType()) == TargetLowering::TypeLegal || TLI.isTypeLegal(Op.getValueType()) || Op.getOpcode() == ISD::TargetConstant) && "Unexpected illegal type!"' failed.
I wonder why both getTypeAction() and isTypeLegal() are called here - shouldn't they be equivalent?
Follow up question is then If the patch looks reasonable: is it enough with just isTypeLegal()?
I also removed the check
if (Ops.size() == LegalVT.getVectorNumElements())
since it seems redundant with
if (ISD::isBuildVectorOfConstantSDNodes(N1.getNode()))
https://reviews.llvm.org/D31651
Files:
lib/CodeGen/SelectionDAG/SelectionDAG.cpp
Index: lib/CodeGen/SelectionDAG/SelectionDAG.cpp
===================================================================
--- lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+++ lib/CodeGen/SelectionDAG/SelectionDAG.cpp
@@ -4126,35 +4126,36 @@
assert(EVT.bitsLE(VT) && "Not extending!");
if (EVT == VT) return N1; // Not actually extending
- auto SignExtendInReg = [&](APInt Val) {
+ auto SignExtendInReg = [&](APInt Val, llvm::EVT ScalarVT) {
unsigned FromBits = EVT.getScalarSizeInBits();
Val <<= Val.getBitWidth() - FromBits;
Val = Val.ashr(Val.getBitWidth() - FromBits);
- return getConstant(Val, DL, VT.getScalarType());
+ return getConstant(Val, DL, ScalarVT);
};
if (N1C) {
const APInt &Val = N1C->getAPIntValue();
- return SignExtendInReg(Val);
+ return SignExtendInReg(Val, VT.getScalarType());
}
if (ISD::isBuildVectorOfConstantSDNodes(N1.getNode())) {
+ // If the scalar type of VT is not legal, keep the original operand type.
+ llvm::EVT LegalScalarVT = (TLI->isTypeLegal(VT.getScalarType()) ?
+ VT.getScalarType() : N1.getOperand(0).getValueType().getScalarType());
+
SmallVector<SDValue, 8> Ops;
for (int i = 0, e = VT.getVectorNumElements(); i != e; ++i) {
SDValue Op = N1.getOperand(i);
- if (Op.isUndef()) {
- Ops.push_back(getUNDEF(VT.getScalarType()));
- continue;
- }
- if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
+ if (Op.isUndef())
+ Ops.push_back(getUNDEF(LegalScalarVT));
+ else {
+ ConstantSDNode *C = cast<ConstantSDNode>(Op);
APInt Val = C->getAPIntValue();
- Val = Val.zextOrTrunc(VT.getScalarSizeInBits());
- Ops.push_back(SignExtendInReg(Val));
+ Val = Val.zextOrTrunc(LegalScalarVT.getSizeInBits());
+ Ops.push_back(SignExtendInReg(Val, LegalScalarVT));
continue;
}
- break;
}
- if (Ops.size() == VT.getVectorNumElements())
- return getBuildVector(VT, DL, Ops);
+ return getBuildVector(VT, DL, Ops);
}
break;
}
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