[PATCH] D31113: [AArch64] Add new subtarget feature to fold LSL into address mode.

[Balaram Makam via Phabricator via llvm-commits]

bmakam marked 2 inline comments as done.
bmakam added a comment.

Thanks for the review Chad,
If there is no objection from others, I will commit this change with the fixes for your comments.



================
Comment at: lib/Target/AArch64/AArch64ISelDAGToDAG.cpp:365
+    return true;
+  if (Subtarget->hasLSLFast() && V.getOpcode() == ISD::ADD) {
+    const SDValue LHS = V.getOperand(0);
----------------
mcrosier wrote:
> Are there other interesting binary operators besides ADD?
One case that is currently not handled by this is when we have extend, for example we fail to fold a logical shift into the addressing mode in the test below for aarch64:

```

define i32 @test3(i32 %base, i32 %base2, i32 %offset) {
entry:
        %tmp1 = shl i32 %offset, 2
        %tmp2 = add i32 %base, %tmp1
        %tmp3 = inttoptr i32 %tmp2 to i32*
        %tmp4 = add i32 %base2, %tmp1
        %tmp5 = inttoptr i32 %tmp4 to i32*
        %tmp6 = load i32, i32* %tmp3
        %tmp7 = load i32, i32* %tmp5
        %tmp8 = add i32 %tmp7, %tmp6
        ret i32 %tmp8
}

```
I think this will have to be fixed in a separate change.


https://reviews.llvm.org/D31113