[PATCH] D31113: [AArch64] Add new subtarget feature to fold LSL into address mode.

[Chad Rosier via Phabricator via llvm-commits]

mcrosier accepted this revision.
mcrosier added a comment.
This revision is now accepted and ready to land.

LGTM, with a few nits.



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Comment at: lib/Target/AArch64/AArch64ISelDAGToDAG.cpp:331
 
+/// \brief Determine whether it is worth to fold SHL into address mode.
+static bool isWorthFoldingSHL(SDValue V) {
----------------
worth it to fold the SHL into the addressing mode.


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Comment at: lib/Target/AArch64/AArch64ISelDAGToDAG.cpp:339
+  unsigned ShiftVal = CSD->getZExtValue();
+  if (ShiftVal > 3)
+    return false;
----------------
I'm not a huge fan of the magic number, but I think it's reasonable to leave as is until another target uses this feature.


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Comment at: lib/Target/AArch64/AArch64ISelDAGToDAG.cpp:360
+    return true;
+  // If a subtarget has a fastpath LSL we can fold logical shift into
+  // address mode and save a cycle.
----------------
we can fold a logical shift into the addressing mode


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Comment at: lib/Target/AArch64/AArch64ISelDAGToDAG.cpp:365
+    return true;
+  if (Subtarget->hasLSLFast() && V.getOpcode() == ISD::ADD) {
+    const SDValue LHS = V.getOperand(0);
----------------
Are there other interesting binary operators besides ADD?


https://reviews.llvm.org/D31113