[PATCH] D31188: [AntiDepBreaker] Do not use getPristineRegs for marking live registers.

[Matthias Braun via Phabricator via llvm-commits]

MatzeB added inline comments.


================
Comment at: llvm/lib/CodeGen/AggressiveAntiDepBreaker.cpp:175
     unsigned Reg = *I;
-    if (!IsReturnBlock && !Pristine.test(Reg)) continue;
-    for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI) {
-      unsigned AliasReg = *AI;
-      State->UnionGroups(AliasReg, 0);
-      KillIndices[AliasReg] = BB->size();
-      DefIndices[AliasReg] = ~0u;
+    if (MFI.isCalleeSavedInfoValid() &&
+        (IsReturnBlock || BB->isLiveIn(Reg) || !HasSlot(Reg))) {
----------------
timshen wrote:
> MatzeB wrote:
> > I don't think this pass will (or should) be used before the prolog epilog inserter so isCalleeSavedInfoValid() should always be true and you could simply assert on it.
> I didn't assert on this, only because of https://github.com/llvm-mirror/llvm/blob/6095a7948d32d712811e8c2ab2190acf8e66a8bc/lib/CodeGen/PrologEpilogInserter.cpp#L66
> 
> It appears that CSInfo is valid only if doSpillCalleeSavedRegs is executed.
> 
> Is it always the case where usesPhysRegsForPEI is necessary for post-RA scheduling?
Ah, that is special behavior for webassembly which keeps using vregs long after register allocation is done. I don't think we should concern ourself with that here as this pass doesn't seem to be compatible with that anyway (a bunch of passes are not and webassembly just isn't using them).


https://reviews.llvm.org/D31188