[PATCH] D31124: AMDGPU/SI: Add lane tracking to SI Scheduler

[Mekhanoshin, Stanislav via llvm-commits]

I think a register can also be partially redefined. E.g. first <def, read-undef>:sub0_sub1, then <def>:sub0. According to the description this is unexpected.

Stas



--- Original message ---
From: Axel Davy via Phabricator <reviews at reviews.llvm.org>
Sent: March 19, 2017 4:15:09 AM
To: axel.davy at ens.fr, timofeev.alexander at gmail.com, Mekhanoshin, Stanislav <Stanislav.Mekhanoshin at amd.com>, Arsenault, Matthew <Matthew.Arsenault at amd.com>
CC: matze at braunis.de, Zhuravlyov, Konstantin <Konstantin.Zhuravlyov at amd.com>, Ding, Wei <Wei.Ding2 at amd.com>, nhaehnle at gmail.com, Liu, Yaxun (Sam) <Yaxun.Liu at amd.com>, Tye, Tony <Tony.Tye at amd.com>, Stuttard, David <David.Stuttard at amd.com>, llvm-commits at lists.llvm.org, tpr.llvm at botech.co.uk, 0xe2.0x9a.0x9b at gmail.com, Rodgers, Gregory <Gregory.Rodgers at amd.com>, Tamazov, Artem <Artem.Tamazov at amd.com>
Subject: [PATCH] D31124: AMDGPU/SI: Add lane tracking to SI Scheduler

> axeldavy created this revision.
> axeldavy added a project: AMDGPU.
> Herald added subscribers: tpr, dstuttard, tony-tye, yaxunl, nhaehnle, wdng, kzhuravl, MatzeB.
>
> This patch adds lane tracking to SI Scheduler.
>
> To handle lanes,
> . When a register is always used with all its lanes, it replaces the register with RegisterMaskPair(Reg, LaneBitMask::all())
> . In the other cases, it determines a 'basis' of masks such that any register/lane usage can be decomposed into fake registers of RegisterMaskPair(Reg, LaneBitMask element of the basis).
>
> Previously the code assumed that a Register cannot be defined if already defined. LaneMasks break this assumption.
> Decomposing into unique RegisterMaskPair "registers" (such that the Lanes don't intersect) enables to reuse the previous assumption.
> A RegisterMaskPair can only be defined if not already alive. Thus enables to use the previous code, with some updates to how register usage is computed.
>
>
> Repository:
>   rL LLVM
>
> https://reviews.llvm.org/D31124
>
> Files:
>   lib/Target/AMDGPU/SIMachineScheduler.cpp
>   lib/Target/AMDGPU/SIMachineScheduler.h
>