[PATCH] D31124: AMDGPU/SI: Add lane tracking to SI Scheduler

[Axel Davy via Phabricator via llvm-commits]

axeldavy created this revision.
axeldavy added a project: AMDGPU.
Herald added subscribers: tpr, dstuttard, tony-tye, yaxunl, nhaehnle, wdng, kzhuravl, MatzeB.

This patch adds lane tracking to SI Scheduler.

To handle lanes,
. When a register is always used with all its lanes, it replaces the register with RegisterMaskPair(Reg, LaneBitMask::all())
. In the other cases, it determines a 'basis' of masks such that any register/lane usage can be decomposed into fake registers of RegisterMaskPair(Reg, LaneBitMask element of the basis).

Previously the code assumed that a Register cannot be defined if already defined. LaneMasks break this assumption.
Decomposing into unique RegisterMaskPair "registers" (such that the Lanes don't intersect) enables to reuse the previous assumption.
A RegisterMaskPair can only be defined if not already alive. Thus enables to use the previous code, with some updates to how register usage is computed.


Repository:
  rL LLVM

https://reviews.llvm.org/D31124

Files:
  lib/Target/AMDGPU/SIMachineScheduler.cpp
  lib/Target/AMDGPU/SIMachineScheduler.h

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