[PATCH] D30829: [Thumb1] combine ADDC/SUBC with a negative immediate
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Wed Mar 15 03:31:37 PDT 2017
This revision was automatically updated to reflect the committed changes.
Closed by commit rL297820: [Thumb1] Fix the bug when adding/subtracting -2147483648 (authored by askrobov).
Changed prior to commit:
https://reviews.llvm.org/D30829?vs=91636&id=91852#toc
Repository:
rL LLVM
https://reviews.llvm.org/D30829
Files:
llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
llvm/trunk/test/CodeGen/Thumb/long.ll
Index: llvm/trunk/test/CodeGen/Thumb/long.ll
===================================================================
--- llvm/trunk/test/CodeGen/Thumb/long.ll
+++ llvm/trunk/test/CodeGen/Thumb/long.ll
@@ -194,3 +194,15 @@
; CHECK: movs r1, r3
}
+; "sub 2147483648" has to be lowered into "add -2147483648"
+define i64 @f12(i64 %x, i64 %y) {
+entry:
+ %tmp1 = sub i64 %x, 2147483648
+ ret i64 %tmp1
+; CHECK-LABEL: f12:
+; CHECK: movs r2, #1
+; CHECK: lsls r2, r2, #31
+; CHECK: movs r3, #0
+; CHECK: adds r0, r0, r2
+; CHECK: sbcs r1, r3
+}
Index: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
===================================================================
--- llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
+++ llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
@@ -9788,8 +9788,8 @@
if (Subtarget->isThumb1Only()) {
SDValue RHS = N->getOperand(1);
if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS)) {
- int64_t imm = C->getSExtValue();
- if (imm < 0) {
+ int32_t imm = C->getSExtValue();
+ if (-imm > 0) {
SDLoc DL(N);
RHS = DAG.getConstant(-imm, DL, MVT::i32);
unsigned Opcode = (N->getOpcode() == ARMISD::ADDC) ? ARMISD::SUBC
@@ -9806,8 +9806,8 @@
if (Subtarget->isThumb1Only()) {
SDValue RHS = N->getOperand(1);
if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS)) {
- int64_t imm = C->getSExtValue();
- if (imm < 0) {
+ int32_t imm = C->getSExtValue();
+ if (-imm > 0) {
SDLoc DL(N);
// The with-carry-in form matches bitwise not instead of the negation.
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