[PATCH] D30829: [Thumb1] combine ADDC/SUBC with a negative immediate

[Z. Zheng via Phabricator via llvm-commits]

zzheng added a comment.

This patch needs to be reverted or appended. I'll try to send a test case.



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Comment at: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp:9671
+        SDLoc DL(N);
+        RHS = DAG.getConstant(-imm, DL, MVT::i32);
+        unsigned Opcode = (N->getOpcode() == ARMISD::ADDC) ? ARMISD::SUBC
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There's a corner case when imm is -2147483648, that's -2^31 and 0x80000000 in two's compliment.

SignExt this value and flip its sign in int64_t, it's still 0x80000000 and interpreted as -2^31 by i32 type.

So we have infinite loop here where this function consume and produce the same node forever.


Repository:
  rL LLVM

https://reviews.llvm.org/D30829