[PATCH] D30910: [SimplifyCFG] allow speculation of div/rem when sibling op exists (PR31028)

[Sanjay Patel via Phabricator via llvm-commits]

spatel added a comment.

In https://reviews.llvm.org/D30910#699943, @efriedma wrote:

> Every CPU can lower divrem to something cheaper than a separate div and rem; that seems fine.
>
> My one concern here is that for a target without a hardware divrem for the width in question, if the rem is inside the conditional, you're speculating a multiply. This is fine if it gets lowered to a hardware instruction, but might be problematic if it gets lowered to a libcall.


Right - I figured I was close to the edge for the hoisting rem case. I see 3 possible solutions:

1. Fix that up in CGP (the despeculation machinery already exists for things like llvm.cttz).
2. Limit the transform to legal ops/types here in SimplifyCFG (TTI should give us that?)
3. Don't hoist rem in this patch, just div. We would still catch the case in the bug report.

Any prefs or other options?


https://reviews.llvm.org/D30910