[PATCH] D30910: [SimplifyCFG] allow speculation of div/rem when sibling op exists (PR31028)

[Eli Friedman via Phabricator via llvm-commits]

efriedma added a comment.

Every CPU can lower divrem to something cheaper than a separate div and rem; that seems fine.

My one concern here is that for a target without a hardware divrem for the width in question, if the rem is inside the conditional, you're speculating a multiply. This is fine if it gets lowered to a hardware instruction, but might be problematic if it gets lowered to a libcall.


https://reviews.llvm.org/D30910