[PATCH] D30744: Improve machine schedulers for in-order processors

[Javed Absar via Phabricator via llvm-commits]

javed.absar added a comment.

In https://reviews.llvm.org/D30744#696106, @atrick wrote:

> I think what Matthias was getting at is that you can add a new ProcResource to model issue constraints. If you have a dual issue machine then any instruction that can't be grouped would simply consume both issue resources. Another option might be to use the begin/end group flags.
>
> A SingleIssue flag seems like special casing a problem that needs a general solution.


For those of us quite familiar with  the scheduler,  using  your suggested approach would indeed be a workaround. However, for those not so familiar,  but wanting to use machine-scheduler to model their sub-target, the natural way to see ProcResource is as a resource (to do something e.g. perform an add). Using resource to impose restriction on instructions is bit counter-intuitive, and would not occur naturally at first. The sad consequence is - this aspect of the pipeline would not be properly or at all modeled.

In https://reviews.llvm.org/D30744#696136, @MatzeB wrote:

> I guess this could still be modeled by making the instruction occupy every processor resource. So I was wondering whether we need the extension of the scheduling model.


Good idea. Unfortunately a syntatic-sugar  that adds 'every processor resource' would not work. For example, if div is not-pipelined and is in execution; then an instruction X that does not need UniDiv but is single issue cannot be issued and has to wait for div to finish.
 Besides, workarounds destroy simplicity/elegance and having a straightforward bit 'isSingleIssue' that is simple to interpret for anyone and does exactly what it says, would possibly be better.


https://reviews.llvm.org/D30744