[PATCH] D30744: Improve machine schedulers for in-order processors

[Matthias Braun via Phabricator via llvm-commits]

MatzeB added a comment.

> The single-issue restriction is on the instruction and not a limitation of the ProcResource e.g. for some processor, a load using load/store unit may be allowed dual-issue, but VLDx using the same load/store unit may not be allowed to dual-issue.

I guess this could still be modeled by making the instruction occupy every processor resource. So I was wondering whether we need the extension of the scheduling model.

In https://reviews.llvm.org/D30744#696124, @atrick wrote:

> That said, if there are multiple target maintainers who think adding a special SingleIssue case would be much better than the alternatives, then it may be worth adding.


We could also make the SingleIssue flag syntactic sugar so tablegen adds all available proc resources to the instruction.


https://reviews.llvm.org/D30744