[PATCH] D30692: [ARM] Correct handling of LSL #0 in an IT block

[John Brawn via Phabricator via llvm-commits]

john.brawn created this revision.
Herald added a subscriber: aemerson.

The check for LSL #0 in an IT block was checking if operand 4 was zero, but operand 4 is the condition code operand so it was actually checking for LSLEQ. Fix this by checking operand 3, which really is the immediate operand, and add some tests.


Repository:
  rL LLVM

https://reviews.llvm.org/D30692

Files:
  lib/Target/ARM/AsmParser/ARMAsmParser.cpp
  test/MC/ARM/lsl-zero.s


Index: test/MC/ARM/lsl-zero.s
===================================================================
--- test/MC/ARM/lsl-zero.s
+++ test/MC/ARM/lsl-zero.s
@@ -122,19 +122,33 @@
         itt eq
         lsleq  r0, r1, #0
         lslseq r0, r1, #0
+        itt gt
+        lslgt  r0, r1, #0
+        lslsgt r0, r1, #0
 
 // CHECK-NONARM: moveq.w r0, r1         @ encoding: [0x4f,0xea,0x01,0x00]
 // CHECK-NONARM: movseq.w r0, r1        @ encoding: [0x5f,0xea,0x01,0x00]
+// CHECK-NONARM: movgt.w r0, r1         @ encoding: [0x4f,0xea,0x01,0x00]
+// CHECK-NONARM: movsgt.w r0, r1        @ encoding: [0x5f,0xea,0x01,0x00]
 
 // CHECK-ARM: moveq r0, r1              @ encoding: [0x01,0x00,0xa0,0x01]
 // CHECK-ARM: movseq r0, r1             @ encoding: [0x01,0x00,0xb0,0x01]
+// CHECK-ARM: movgt r0, r1              @ encoding: [0x01,0x00,0xa0,0xc1]
+// CHECK-ARM: movsgt r0, r1             @ encoding: [0x01,0x00,0xb0,0xc1]
 
         itt eq
         moveq  r0, r1, lsl #0
         movseq r0, r1, lsl #0
+        itt gt
+        movgt  r0, r1, lsl #0
+        movsgt r0, r1, lsl #0
 
 // CHECK-NONARM: moveq.w r0, r1         @ encoding: [0x4f,0xea,0x01,0x00]
 // CHECK-NONARM: movseq.w r0, r1        @ encoding: [0x5f,0xea,0x01,0x00]
+// CHECK-NONARM: movgt.w r0, r1         @ encoding: [0x4f,0xea,0x01,0x00]
+// CHECK-NONARM: movsgt.w r0, r1        @ encoding: [0x5f,0xea,0x01,0x00]
 
 // CHECK-ARM: moveq r0, r1              @ encoding: [0x01,0x00,0xa0,0x01]
 // CHECK-ARM: movseq r0, r1             @ encoding: [0x01,0x00,0xb0,0x01]
+// CHECK-ARM: movgt r0, r1              @ encoding: [0x01,0x00,0xa0,0xc1]
+// CHECK-ARM: movsgt r0, r1             @ encoding: [0x01,0x00,0xb0,0xc1]
Index: lib/Target/ARM/AsmParser/ARMAsmParser.cpp
===================================================================
--- lib/Target/ARM/AsmParser/ARMAsmParser.cpp
+++ lib/Target/ARM/AsmParser/ARMAsmParser.cpp
@@ -8940,7 +8940,7 @@
         inITBlock())
       return Match_RequiresNotITBlock;
     // LSL with zero immediate is not allowed in an IT block
-    if (Opc == ARM::tLSLri && Inst.getOperand(4).getImm() == 0 && inITBlock())
+    if (Opc == ARM::tLSLri && Inst.getOperand(3).getImm() == 0 && inITBlock())
       return Match_RequiresNotITBlock;
   } else if (isThumbOne()) {
     // Some high-register supporting Thumb1 encodings only allow both registers


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