[llvm] r297141 - [Hexagon] Do not insert instructions before PHI nodes

[Krzysztof Parzyszek via llvm-commits]

Author: kparzysz
Date: Tue Mar  7 08:20:19 2017
New Revision: 297141

URL: http://llvm.org/viewvc/llvm-project?rev=297141&view=rev
Log:
[Hexagon] Do not insert instructions before PHI nodes

Modified:
    llvm/trunk/lib/Target/Hexagon/HexagonBitSimplify.cpp
    llvm/trunk/test/CodeGen/Hexagon/bit-phi.ll

Modified: llvm/trunk/lib/Target/Hexagon/HexagonBitSimplify.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonBitSimplify.cpp?rev=297141&r1=297140&r2=297141&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonBitSimplify.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonBitSimplify.cpp Tue Mar  7 08:20:19 2017
@@ -2375,7 +2375,9 @@ bool BitSimplification::simplifyExtractL
     DebugLoc DL = MI->getDebugLoc();
     MachineBasicBlock &B = *MI->getParent();
     unsigned NewR = MRI.createVirtualRegister(FRC);
-    auto MIB = BuildMI(B, MI, DL, HII.get(ExtOpc), NewR)
+    auto At = MI->isPHI() ? B.getFirstNonPHI()
+                          : MachineBasicBlock::iterator(MI);
+    auto MIB = BuildMI(B, At, DL, HII.get(ExtOpc), NewR)
                   .addReg(R, 0, SR);
     switch (ExtOpc) {
       case Hexagon::A2_sxtb:

Modified: llvm/trunk/test/CodeGen/Hexagon/bit-phi.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/bit-phi.ll?rev=297141&r1=297140&r2=297141&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Hexagon/bit-phi.ll (original)
+++ llvm/trunk/test/CodeGen/Hexagon/bit-phi.ll Tue Mar  7 08:20:19 2017
@@ -1,4 +1,5 @@
 ; RUN: llc -march=hexagon < %s
+; RUN: llc -march=hexagon -disable-hcp < %s
 ; REQUIRES: asserts
 
 target datalayout = "e-m:e-p:32:32-i1:32-i64:64-a:0-v32:32-n16:32"