[PATCH] D30355: [ARM] don't transform an add(ext Cond), C to select unless there's a setcc of the condition

[Eli Friedman via Phabricator via llvm-commits]

efriedma added a comment.

> Selecting condition-flag-setting instructions (ands/adds) in "test_tst_assessment" may be a separate bug?

That testcase definitely isn't testing what it's supposed to test anymore.  Can you change it to generate approximately the same code as before?  (Basically something like "a &= 3; return b & 3 ? a : a-1;".)

The change essentially looks fine; the point of the transform is to favor a predicated operation over a predicated mov, but that only makes sense if we were actually going to generate a predicated move in the first place.



================
Comment at: lib/Target/ARM/ARMISelLowering.cpp:9166
     CC = N->getOperand(0);
-    if (CC.getValueType() != MVT::i1)
+    if (!CC.getNode() || CC.getOpcode() != ISD::SETCC ||
+        CC.getValueType() != MVT::i1)
----------------
How can "!CC.getNode()" possibly be true?  CC was just set on the previous line.


https://reviews.llvm.org/D30355