[PATCH] D30355: [ARM] don't transform an add(ext Cond), C to select unless there's a setcc of the condition

[Sanjay Patel via Phabricator via llvm-commits]

spatel created this revision.
Herald added subscribers: mcrosier, aemerson.

The transform in question claims to be doing:

  // fold (add (select cc, 0, c), x) -> (select cc, x, (add, x, c))

...starting in PerformADDCombineWithOperands(), but it wasn't actually checking for a setcc node for the sext/zext patterns.

This is exactly the opposite of a transform I'd like to add to DAGCombiner's foldSelectOfConstants(), so I was seeing infinite loops with my draft of a patch applied.

Selecting condition-flag-setting instructions (ands/adds) in "test_tst_assessment" may be a separate bug?


https://reviews.llvm.org/D30355

Files:
  lib/Target/ARM/ARMISelLowering.cpp
  test/CodeGen/ARM/arm-and-tst-peephole.ll
  test/CodeGen/ARM/select_const.ll


Index: test/CodeGen/ARM/select_const.ll
===================================================================
--- test/CodeGen/ARM/select_const.ll
+++ test/CodeGen/ARM/select_const.ll
@@ -98,9 +98,8 @@
 define i32 @select_0_or_neg1_alt(i1 %cond) {
 ; CHECK-LABEL: select_0_or_neg1_alt:
 ; CHECK:       @ BB#0:
-; CHECK-NEXT:    mov r1, #1
-; CHECK-NEXT:    bic r0, r1, r0
-; CHECK-NEXT:    rsb r0, r0, #0
+; CHECK-NEXT:    and r0, r0, #1
+; CHECK-NEXT:    sub r0, r0, #1
 ; CHECK-NEXT:    mov pc, lr
   %z = zext i1 %cond to i32
   %add = add i32 %z, -1
@@ -110,8 +109,7 @@
 define i32 @select_0_or_neg1_alt_zeroext(i1 zeroext %cond) {
 ; CHECK-LABEL: select_0_or_neg1_alt_zeroext:
 ; CHECK:       @ BB#0:
-; CHECK-NEXT:    eor r0, r0, #1
-; CHECK-NEXT:    rsb r0, r0, #0
+; CHECK-NEXT:    sub r0, r0, #1
 ; CHECK-NEXT:    mov pc, lr
   %z = zext i1 %cond to i32
   %add = add i32 %z, -1
Index: test/CodeGen/ARM/arm-and-tst-peephole.ll
===================================================================
--- test/CodeGen/ARM/arm-and-tst-peephole.ll
+++ test/CodeGen/ARM/arm-and-tst-peephole.ll
@@ -143,38 +143,31 @@
 define i32 @test_tst_assessment(i1 %lhs, i1 %rhs) {
 ; ARM-LABEL: test_tst_assessment:
 ; ARM:       @ BB#0:
+; ARM-NEXT:    and r1, r1, #1
 ; ARM-NEXT:    and r0, r0, #1
-; ARM-NEXT:    tst r1, #1
-; ARM-NEXT:    subne r0, r0, #1
+; ARM-NEXT:    sub r0, r0, r1
 ; ARM-NEXT:    mov pc, lr
 ;
 ; THUMB-LABEL: test_tst_assessment:
 ; THUMB:       @ BB#0:
 ; THUMB-NEXT:    movs r2, #1
-; THUMB-NEXT:    ands r2, r0
-; THUMB-NEXT:    subs r0, r2, #1
-; THUMB-NEXT:    lsls r1, r1, #31
-; THUMB-NEXT:    bne .LBB2_2
-; THUMB-NEXT:  @ BB#1:
-; THUMB-NEXT:    push {r2}
-; THUMB-NEXT:    pop {r0}
-; THUMB-NEXT:  .LBB2_2:
+; THUMB-NEXT:    ands r1, r2
+; THUMB-NEXT:    ands r0, r2
+; THUMB-NEXT:    subs r0, r0, r1
 ; THUMB-NEXT:    bx lr
 ;
 ; T2-LABEL: test_tst_assessment:
 ; T2:       @ BB#0:
-; T2-NEXT:    lsls r1, r1, #31
+; T2-NEXT:    and r1, r1, #1
 ; T2-NEXT:    and r0, r0, #1
-; T2-NEXT:    it ne
-; T2-NEXT:    subne r0, #1
+; T2-NEXT:    subs r0, r0, r1
 ; T2-NEXT:    bx lr
 ;
 ; V8-LABEL: test_tst_assessment:
 ; V8:       @ BB#0:
-; V8-NEXT:    lsls r1, r1, #31
+; V8-NEXT:    and r1, r1, #1
 ; V8-NEXT:    and r0, r0, #1
-; V8-NEXT:    it ne
-; V8-NEXT:    subne r0, #1
+; V8-NEXT:    subs r0, r0, r1
 ; V8-NEXT:    bx lr
   %lhs32 = zext i1 %lhs to i32
   %rhs32 = zext i1 %rhs to i32
Index: lib/Target/ARM/ARMISelLowering.cpp
===================================================================
--- lib/Target/ARM/ARMISelLowering.cpp
+++ lib/Target/ARM/ARMISelLowering.cpp
@@ -9163,7 +9163,8 @@
     SDLoc dl(N);
     EVT VT = N->getValueType(0);
     CC = N->getOperand(0);
-    if (CC.getValueType() != MVT::i1)
+    if (!CC.getNode() || CC.getOpcode() != ISD::SETCC ||
+        CC.getValueType() != MVT::i1)
       return false;
     Invert = !AllOnes;
     if (AllOnes)


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