[llvm] r295970 - [X86][AVX] Disable VCVTSS2SD & VCVTSD2SS memory folding and fix the register class of their first input when creating node in fast-isel.

Fri Feb 24 09:49:59 PST 2017

Hi Ayman

Greendragon is still failing on -verify-machineinstr after this fix. The error message goes from:
*** Bad machine code: Illegal virtual register for instruction ***
- function:    __scalar_test_op
- basic block: BB#3 for scalar_op_vrcpps_324.s0.x (0x7fe20107cca8)
- instruction: %vreg55<def> = VCVTSS2SDrr
- operand 1:   %vreg54
Expected a FR64 register, but got a FR32 register
fatal error: error in backend: Found 1 machine code errors.
 <>

To:

*** Bad machine code: Virtual register defs don't dominate all uses. ***
- function:    __scalar_test_op
- v. register: %vreg56
fatal error: error in backend: Found 1 machine code errors.
 <>

http://lab.llvm.org:8080/green/job/Compiler_Verifiers/6430/ <http://lab.llvm.org:8080/green/job/Compiler_Verifiers/6430/>

Can you take a look?

Steven

> On Feb 23, 2017, at 5:15 AM, Ayman Musa via llvm-commits <llvm-commits at lists.llvm.org> wrote:
> 
> Author: aymanmus
> Date: Thu Feb 23 07:15:44 2017
> New Revision: 295970
> 
> URL: http://llvm.org/viewvc/llvm-project?rev=295970&view=rev
> Log:
> [X86][AVX] Disable VCVTSS2SD & VCVTSD2SS memory folding and fix the register class of their first input when creating node in fast-isel.
> 
> (Quick fix to buildbot failure after rL295940 commit).
> 
> 
> Modified:
>    llvm/trunk/lib/Target/X86/X86FastISel.cpp
>    llvm/trunk/lib/Target/X86/X86InstrInfo.cpp
>    llvm/trunk/test/CodeGen/X86/avx-cvt.ll
>    llvm/trunk/test/CodeGen/X86/stack-folding-fp-avx1.ll
> 
> Modified: llvm/trunk/lib/Target/X86/X86FastISel.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86FastISel.cpp?rev=295970&r1=295969&r2=295970&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/X86/X86FastISel.cpp (original)
> +++ llvm/trunk/lib/Target/X86/X86FastISel.cpp Thu Feb 23 07:15:44 2017
> @@ -2427,8 +2427,13 @@ bool X86FastISel::X86SelectFPExtOrFPTrun
>   MachineInstrBuilder MIB;
>   MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(TargetOpc),
>                 ResultReg);
> -  if (Subtarget->hasAVX())
> -    MIB.addReg(OpReg);
> +  if (Subtarget->hasAVX()) {
> +    unsigned ImplicitDefReg = createResultReg(RC);
> +    BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
> +            TII.get(TargetOpcode::IMPLICIT_DEF), ImplicitDefReg);
> +
> +    MIB.addReg(ImplicitDefReg);
> +  }
>   MIB.addReg(OpReg);
>   updateValueMap(I, ResultReg);
>   return true;
> 
> Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.cpp?rev=295970&r1=295969&r2=295970&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/X86/X86InstrInfo.cpp (original)
> +++ llvm/trunk/lib/Target/X86/X86InstrInfo.cpp Thu Feb 23 07:15:44 2017
> @@ -1385,8 +1385,6 @@ X86InstrInfo::X86InstrInfo(X86Subtarget
>     { X86::PMULHRWrr,         X86::PMULHRWrm,         0 },
> 
>     // AVX 128-bit versions of foldable instructions
> -    { X86::VCVTSD2SSrr,       X86::VCVTSD2SSrm,        0 },
> -    { X86::Int_VCVTSD2SSrr,   X86::Int_VCVTSD2SSrm,    TB_NO_REVERSE },
>     { X86::VCVTSI2SD64rr,     X86::VCVTSI2SD64rm,      0 },
>     { X86::Int_VCVTSI2SD64rr, X86::Int_VCVTSI2SD64rm,  0 },
>     { X86::VCVTSI2SDrr,       X86::VCVTSI2SDrm,        0 },
> @@ -1395,8 +1393,6 @@ X86InstrInfo::X86InstrInfo(X86Subtarget
>     { X86::Int_VCVTSI2SS64rr, X86::Int_VCVTSI2SS64rm,  0 },
>     { X86::VCVTSI2SSrr,       X86::VCVTSI2SSrm,        0 },
>     { X86::Int_VCVTSI2SSrr,   X86::Int_VCVTSI2SSrm,    0 },
> -    { X86::VCVTSS2SDrr,       X86::VCVTSS2SDrm,        0 },
> -    { X86::Int_VCVTSS2SDrr,   X86::Int_VCVTSS2SDrm,    TB_NO_REVERSE },
>     { X86::VADDPDrr,          X86::VADDPDrm,           0 },
>     { X86::VADDPSrr,          X86::VADDPSrm,           0 },
>     { X86::VADDSDrr,          X86::VADDSDrm,           0 },
> 
> Modified: llvm/trunk/test/CodeGen/X86/avx-cvt.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx-cvt.ll?rev=295970&r1=295969&r2=295970&view=diff
> ==============================================================================
> --- llvm/trunk/test/CodeGen/X86/avx-cvt.ll (original)
> +++ llvm/trunk/test/CodeGen/X86/avx-cvt.ll Thu Feb 23 07:15:44 2017
> @@ -136,7 +136,8 @@ define float @funcD(i64* nocapture %e) n
> define void @fpext() nounwind uwtable {
> ; CHECK-LABEL: fpext:
> ; CHECK:       # BB#0:
> -; CHECK-NEXT:    vcvtss2sd -{{[0-9]+}}(%rsp), %xmm0, %xmm0
> +; CHECK-NEXT:    vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
> +; CHECK-NEXT:    vcvtss2sd %xmm0, %xmm0, %xmm0
> ; CHECK-NEXT:    vmovsd %xmm0, -{{[0-9]+}}(%rsp)
> ; CHECK-NEXT:    retq
>   %f = alloca float, align 4
> 
> Modified: llvm/trunk/test/CodeGen/X86/stack-folding-fp-avx1.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/stack-folding-fp-avx1.ll?rev=295970&r1=295969&r2=295970&view=diff
> ==============================================================================
> --- llvm/trunk/test/CodeGen/X86/stack-folding-fp-avx1.ll (original)
> +++ llvm/trunk/test/CodeGen/X86/stack-folding-fp-avx1.ll Thu Feb 23 07:15:44 2017
> @@ -575,17 +575,6 @@ define i64 @stack_fold_cvtsd2si64_int(<2
> }
> declare i64 @llvm.x86.sse2.cvtsd2si64(<2 x double>) nounwind readnone
> 
> -; TODO stack_fold_cvtsd2ss
> -
> -define <4 x float> @stack_fold_cvtsd2ss_int(<2 x double> %a0) {
> -  ;CHECK-LABEL: stack_fold_cvtsd2ss_int
> -  ;CHECK:  vcvtsd2ss {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}}, {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
> -  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
> -  %2 = call <4 x float> @llvm.x86.sse2.cvtsd2ss(<4 x float> <float 0x0, float 0x0, float 0x0, float 0x0>, <2 x double> %a0)
> -  ret <4 x float> %2
> -}
> -declare <4 x float> @llvm.x86.sse2.cvtsd2ss(<4 x float>, <2 x double>) nounwind readnone
> -
> define double @stack_fold_cvtsi2sd(i32 %a0) {
>   ;CHECK-LABEL: stack_fold_cvtsi2sd
>   ;CHECK:  vcvtsi2sdl {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}}, {{%xmm[0-9][0-9]*}} {{.*#+}} 4-byte Folded Reload
> @@ -654,17 +643,6 @@ define <4 x float> @stack_fold_cvtsi642s
> }
> declare <4 x float> @llvm.x86.sse.cvtsi642ss(<4 x float>, i64) nounwind readnone
> 
> -; TODO stack_fold_cvtss2sd
> -
> -define <2 x double> @stack_fold_cvtss2sd_int(<4 x float> %a0) {
> -  ;CHECK-LABEL: stack_fold_cvtss2sd_int
> -  ;CHECK:  vcvtss2sd {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}}, {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
> -  %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
> -  %2 = call <2 x double> @llvm.x86.sse2.cvtss2sd(<2 x double> <double 0x0, double 0x0>, <4 x float> %a0)
> -  ret <2 x double> %2
> -}
> -declare <2 x double> @llvm.x86.sse2.cvtss2sd(<2 x double>, <4 x float>) nounwind readnone
> -
> ; TODO stack_fold_cvtss2si
> 
> define i32 @stack_fold_cvtss2si_int(<4 x float> %a0) {
> 
> 
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