<html><head><meta http-equiv="Content-Type" content="text/html charset=us-ascii"></head><body style="word-wrap: break-word; -webkit-nbsp-mode: space; -webkit-line-break: after-white-space;" class="">Hi Ayman<div class=""><br class=""></div><div class="">Greendragon is still failing on -verify-machineinstr after this fix. The error message goes from:</div><div class=""><span style="color: rgb(51, 51, 51); font-family: monospace; font-size: 13px; white-space: pre-wrap;" class="">*** Bad machine code: Illegal virtual register for instruction ***
- function: __scalar_test_op
- basic block: BB#3 for scalar_op_vrcpps_324.s0.x (0x7fe20107cca8)
- instruction: %vreg55<def> = VCVTSS2SDrr
- operand 1: %vreg54
Expected a FR64 register, but got a FR32 register
fatal error: error in backend: Found 1 machine code errors.
</span><a id="86519426149ba4694-19c4-4d7e-bec5-911270d8a58c" style="box-sizing: border-box; word-wrap: break-word; color: rgb(51, 51, 51); font-family: monospace; font-size: 13px; white-space: pre-wrap; display: block; position: relative; top: -2em; visibility: hidden;" class=""></a><span title="Compile Error" style="box-sizing: border-box; font-family: monospace; font-size: 13px; white-space: pre-wrap; color: white; background-color: red;" class=""></span></div><div class=""><span style="color: rgb(51, 51, 51); font-family: monospace; font-size: 13px; white-space: pre-wrap;" class=""><br class=""></span></div><div class="">To:</div><div class=""><br class=""></div><div class=""><span style="color: rgb(51, 51, 51); font-family: monospace; font-size: 13px; white-space: pre-wrap;" class="">*** Bad machine code: Virtual register defs don't dominate all uses. ***
- function: __scalar_test_op
- v. register: %vreg56
fatal error: error in backend: Found 1 machine code errors.
</span><a id="86519426149ba4694-19c4-4d7e-bec5-911270d8a58c" style="box-sizing: border-box; word-wrap: break-word; color: rgb(51, 51, 51); font-family: monospace; font-size: 13px; white-space: pre-wrap; display: block; position: relative; top: -2em; visibility: hidden;" class=""></a><span title="Compile Error" style="box-sizing: border-box; font-family: monospace; font-size: 13px; white-space: pre-wrap; color: white; background-color: red;" class=""></span></div><div class=""><span style="color: rgb(51, 51, 51); font-family: monospace; font-size: 13px; white-space: pre-wrap;" class=""><br class=""></span></div><div class=""><br class=""></div><div class=""><a href="http://lab.llvm.org:8080/green/job/Compiler_Verifiers/6430/" class="">http://lab.llvm.org:8080/green/job/Compiler_Verifiers/6430/</a></div><div class=""><br class=""></div><div class="">Can you take a look?</div><div class=""><br class=""></div><div class="">Steven</div><div class=""><br class=""><div><blockquote type="cite" class=""><div class="">On Feb 23, 2017, at 5:15 AM, Ayman Musa via llvm-commits <<a href="mailto:llvm-commits@lists.llvm.org" class="">llvm-commits@lists.llvm.org</a>> wrote:</div><br class="Apple-interchange-newline"><div class=""><div class="">Author: aymanmus<br class="">Date: Thu Feb 23 07:15:44 2017<br class="">New Revision: 295970<br class=""><br class="">URL: <a href="http://llvm.org/viewvc/llvm-project?rev=295970&view=rev" class="">http://llvm.org/viewvc/llvm-project?rev=295970&view=rev</a><br class="">Log:<br class="">[X86][AVX] Disable VCVTSS2SD & VCVTSD2SS memory folding and fix the register class of their first input when creating node in fast-isel.<br class=""><br class="">(Quick fix to buildbot failure after rL295940 commit).<br class=""><br class=""><br class="">Modified:<br class=""> llvm/trunk/lib/Target/X86/X86FastISel.cpp<br class=""> llvm/trunk/lib/Target/X86/X86InstrInfo.cpp<br class=""> llvm/trunk/test/CodeGen/X86/avx-cvt.ll<br class=""> llvm/trunk/test/CodeGen/X86/stack-folding-fp-avx1.ll<br class=""><br class="">Modified: llvm/trunk/lib/Target/X86/X86FastISel.cpp<br class="">URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86FastISel.cpp?rev=295970&r1=295969&r2=295970&view=diff" class="">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86FastISel.cpp?rev=295970&r1=295969&r2=295970&view=diff</a><br class="">==============================================================================<br class="">--- llvm/trunk/lib/Target/X86/X86FastISel.cpp (original)<br class="">+++ llvm/trunk/lib/Target/X86/X86FastISel.cpp Thu Feb 23 07:15:44 2017<br class="">@@ -2427,8 +2427,13 @@ bool X86FastISel::X86SelectFPExtOrFPTrun<br class=""> MachineInstrBuilder MIB;<br class=""> MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(TargetOpc),<br class=""> ResultReg);<br class="">- if (Subtarget->hasAVX())<br class="">- MIB.addReg(OpReg);<br class="">+ if (Subtarget->hasAVX()) {<br class="">+ unsigned ImplicitDefReg = createResultReg(RC);<br class="">+ BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,<br class="">+ TII.get(TargetOpcode::IMPLICIT_DEF), ImplicitDefReg);<br class="">+<br class="">+ MIB.addReg(ImplicitDefReg);<br class="">+ }<br class=""> MIB.addReg(OpReg);<br class=""> updateValueMap(I, ResultReg);<br class=""> return true;<br class=""><br class="">Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.cpp<br class="">URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.cpp?rev=295970&r1=295969&r2=295970&view=diff" class="">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.cpp?rev=295970&r1=295969&r2=295970&view=diff</a><br class="">==============================================================================<br class="">--- llvm/trunk/lib/Target/X86/X86InstrInfo.cpp (original)<br class="">+++ llvm/trunk/lib/Target/X86/X86InstrInfo.cpp Thu Feb 23 07:15:44 2017<br class="">@@ -1385,8 +1385,6 @@ X86InstrInfo::X86InstrInfo(X86Subtarget<br class=""> { X86::PMULHRWrr, X86::PMULHRWrm, 0 },<br class=""><br class=""> // AVX 128-bit versions of foldable instructions<br class="">- { X86::VCVTSD2SSrr, X86::VCVTSD2SSrm, 0 },<br class="">- { X86::Int_VCVTSD2SSrr, X86::Int_VCVTSD2SSrm, TB_NO_REVERSE },<br class=""> { X86::VCVTSI2SD64rr, X86::VCVTSI2SD64rm, 0 },<br class=""> { X86::Int_VCVTSI2SD64rr, X86::Int_VCVTSI2SD64rm, 0 },<br class=""> { X86::VCVTSI2SDrr, X86::VCVTSI2SDrm, 0 },<br class="">@@ -1395,8 +1393,6 @@ X86InstrInfo::X86InstrInfo(X86Subtarget<br class=""> { X86::Int_VCVTSI2SS64rr, X86::Int_VCVTSI2SS64rm, 0 },<br class=""> { X86::VCVTSI2SSrr, X86::VCVTSI2SSrm, 0 },<br class=""> { X86::Int_VCVTSI2SSrr, X86::Int_VCVTSI2SSrm, 0 },<br class="">- { X86::VCVTSS2SDrr, X86::VCVTSS2SDrm, 0 },<br class="">- { X86::Int_VCVTSS2SDrr, X86::Int_VCVTSS2SDrm, TB_NO_REVERSE },<br class=""> { X86::VADDPDrr, X86::VADDPDrm, 0 },<br class=""> { X86::VADDPSrr, X86::VADDPSrm, 0 },<br class=""> { X86::VADDSDrr, X86::VADDSDrm, 0 },<br class=""><br class="">Modified: llvm/trunk/test/CodeGen/X86/avx-cvt.ll<br class="">URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx-cvt.ll?rev=295970&r1=295969&r2=295970&view=diff" class="">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx-cvt.ll?rev=295970&r1=295969&r2=295970&view=diff</a><br class="">==============================================================================<br class="">--- llvm/trunk/test/CodeGen/X86/avx-cvt.ll (original)<br class="">+++ llvm/trunk/test/CodeGen/X86/avx-cvt.ll Thu Feb 23 07:15:44 2017<br class="">@@ -136,7 +136,8 @@ define float @funcD(i64* nocapture %e) n<br class=""> define void @fpext() nounwind uwtable {<br class=""> ; CHECK-LABEL: fpext:<br class=""> ; CHECK: # BB#0:<br class="">-; CHECK-NEXT: vcvtss2sd -{{[0-9]+}}(%rsp), %xmm0, %xmm0<br class="">+; CHECK-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero<br class="">+; CHECK-NEXT: vcvtss2sd %xmm0, %xmm0, %xmm0<br class=""> ; CHECK-NEXT: vmovsd %xmm0, -{{[0-9]+}}(%rsp)<br class=""> ; CHECK-NEXT: retq<br class=""> %f = alloca float, align 4<br class=""><br class="">Modified: llvm/trunk/test/CodeGen/X86/stack-folding-fp-avx1.ll<br class="">URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/stack-folding-fp-avx1.ll?rev=295970&r1=295969&r2=295970&view=diff" class="">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/stack-folding-fp-avx1.ll?rev=295970&r1=295969&r2=295970&view=diff</a><br class="">==============================================================================<br class="">--- llvm/trunk/test/CodeGen/X86/stack-folding-fp-avx1.ll (original)<br class="">+++ llvm/trunk/test/CodeGen/X86/stack-folding-fp-avx1.ll Thu Feb 23 07:15:44 2017<br class="">@@ -575,17 +575,6 @@ define i64 @stack_fold_cvtsd2si64_int(<2<br class=""> }<br class=""> declare i64 @llvm.x86.sse2.cvtsd2si64(<2 x double>) nounwind readnone<br class=""><br class="">-; TODO stack_fold_cvtsd2ss<br class="">-<br class="">-define <4 x float> @stack_fold_cvtsd2ss_int(<2 x double> %a0) {<br class="">- ;CHECK-LABEL: stack_fold_cvtsd2ss_int<br class="">- ;CHECK: vcvtsd2ss {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}}, {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload<br class="">- %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()<br class="">- %2 = call <4 x float> @llvm.x86.sse2.cvtsd2ss(<4 x float> <float 0x0, float 0x0, float 0x0, float 0x0>, <2 x double> %a0)<br class="">- ret <4 x float> %2<br class="">-}<br class="">-declare <4 x float> @llvm.x86.sse2.cvtsd2ss(<4 x float>, <2 x double>) nounwind readnone<br class="">-<br class=""> define double @stack_fold_cvtsi2sd(i32 %a0) {<br class=""> ;CHECK-LABEL: stack_fold_cvtsi2sd<br class=""> ;CHECK: vcvtsi2sdl {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}}, {{%xmm[0-9][0-9]*}} {{.*#+}} 4-byte Folded Reload<br class="">@@ -654,17 +643,6 @@ define <4 x float> @stack_fold_cvtsi642s<br class=""> }<br class=""> declare <4 x float> @llvm.x86.sse.cvtsi642ss(<4 x float>, i64) nounwind readnone<br class=""><br class="">-; TODO stack_fold_cvtss2sd<br class="">-<br class="">-define <2 x double> @stack_fold_cvtss2sd_int(<4 x float> %a0) {<br class="">- ;CHECK-LABEL: stack_fold_cvtss2sd_int<br class="">- ;CHECK: vcvtss2sd {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}}, {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload<br class="">- %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()<br class="">- %2 = call <2 x double> @llvm.x86.sse2.cvtss2sd(<2 x double> <double 0x0, double 0x0>, <4 x float> %a0)<br class="">- ret <2 x double> %2<br class="">-}<br class="">-declare <2 x double> @llvm.x86.sse2.cvtss2sd(<2 x double>, <4 x float>) nounwind readnone<br class="">-<br class=""> ; TODO stack_fold_cvtss2si<br class=""><br class=""> define i32 @stack_fold_cvtss2si_int(<4 x float> %a0) {<br class=""><br class=""><br class="">_______________________________________________<br class="">llvm-commits mailing list<br class=""><a href="mailto:llvm-commits@lists.llvm.org" class="">llvm-commits@lists.llvm.org</a><br class="">http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-commits<br class=""></div></div></blockquote></div><br class=""></div></body></html>