[llvm] r295306 - [ARM] GlobalISel: Add reg bank mappings for G_SEQUENCE and G_EXTRACT

[Diana Picus via llvm-commits]

I added some checks in r295441, I hope that addresses your concerns.
Please let me know if it doesn't :)

Thanks,
Diana

On 17 February 2017 at 10:34, Diana Picus <diana.picus at linaro.org> wrote:
> On 17 February 2017 at 02:31, Quentin Colombet <qcolombet at apple.com> wrote:
>> Hi Diana,
>>
>>> On Feb 16, 2017, at 3:00 AM, Diana Picus via llvm-commits <llvm-commits at lists.llvm.org> wrote:
>>>
>>> Author: rovka
>>> Date: Thu Feb 16 05:00:31 2017
>>> New Revision: 295306
>>>
>>> URL: http://llvm.org/viewvc/llvm-project?rev=295306&view=rev
>>> Log:
>>> [ARM] GlobalISel: Add reg bank mappings for G_SEQUENCE and G_EXTRACT
>>>
>>> Support G_SEQUENCE and G_EXTRACT as needed for passing double precision floating
>>> point values in the soft-fp float mode.
>>>
>>> Modified:
>>>    llvm/trunk/lib/Target/ARM/ARMRegisterBankInfo.cpp
>>>    llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-regbankselect.mir
>>>
>>> Modified: llvm/trunk/lib/Target/ARM/ARMRegisterBankInfo.cpp
>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMRegisterBankInfo.cpp?rev=295306&r1=295305&r2=295306&view=diff
>>> ==============================================================================
>>> --- llvm/trunk/lib/Target/ARM/ARMRegisterBankInfo.cpp (original)
>>> +++ llvm/trunk/lib/Target/ARM/ARMRegisterBankInfo.cpp Thu Feb 16 05:00:31 2017
>>> @@ -143,6 +143,32 @@ ARMRegisterBankInfo::getInstrMapping(con
>>>   case G_FRAME_INDEX:
>>>     OperandsMapping = getOperandsMapping({&ARM::ValueMappings[0], nullptr});
>>>     break;
>>> +  case G_SEQUENCE: {
>>> +    // We only support G_SEQUENCE for creating a double precision floating point
>>> +    // value out of two GPRs.
>>> +    LLT Ty1 = MRI.getType(MI.getOperand(1).getReg());
>>> +    LLT Ty2 = MRI.getType(MI.getOperand(3).getReg());
>>> +    if (Ty.getSizeInBits() != 64 || Ty1.getSizeInBits() != 32 ||
>>> +        Ty2.getSizeInBits() != 32)
>>> +      return InstructionMapping{};
>>> +    OperandsMapping =
>>> +        getOperandsMapping({&ARM::ValueMappings[6], &ARM::ValueMappings[0],
>>> +                            nullptr, &ARM::ValueMappings[0], nullptr});
>>
>> Could you use enum or some other sort of constant instead of hardcoded numbers for the indices of the ValueMappings?
>
> Sure, I'll look into it, thanks for suggesting!
>
>>
>> Otherwise I am afraid we might silently great that when the mapping gets generated by tablegen.
>>
>> Cheers,
>> -Quentin
>>
>>> +    break;
>>> +  }
>>> +  case G_EXTRACT: {
>>> +    // We only support G_EXTRACT for splitting a double precision floating point
>>> +    // value into two GPRs.
>>> +    LLT Ty1 = MRI.getType(MI.getOperand(1).getReg());
>>> +    LLT Ty2 = MRI.getType(MI.getOperand(2).getReg());
>>> +    if (Ty.getSizeInBits() != 32 || Ty1.getSizeInBits() != 32 ||
>>> +        Ty2.getSizeInBits() != 64)
>>> +      return InstructionMapping{};
>>> +    OperandsMapping =
>>> +        getOperandsMapping({&ARM::ValueMappings[0], &ARM::ValueMappings[0],
>>> +                            &ARM::ValueMappings[6], nullptr, nullptr});
>>> +    break;
>>> +  }
>>>   default:
>>>     return InstructionMapping{};
>>>   }
>>>
>>> Modified: llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-regbankselect.mir
>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-regbankselect.mir?rev=295306&r1=295305&r2=295306&view=diff
>>> ==============================================================================
>>> --- llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-regbankselect.mir (original)
>>> +++ llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-regbankselect.mir Thu Feb 16 05:00:31 2017
>>> @@ -9,6 +9,8 @@
>>>
>>>   define void @test_fadd_s32() { ret void }
>>>   define void @test_fadd_s64() { ret void }
>>> +
>>> +  define void @test_soft_fp_s64() { ret void }
>>> ...
>>> ---
>>> name:            test_add_s32
>>> @@ -202,5 +204,35 @@ body:             |
>>>     BX_RET 14, _, implicit %d0
>>>
>>> ...
>>> +---
>>> +name:            test_soft_fp_s64
>>> +# CHECK-LABEL: name: test_soft_fp_s64
>>> +legalized:       true
>>> +regBankSelected: false
>>> +selected:        false
>>> +# CHECK: registers:
>>> +# CHECK: - { id: 0, class: gprb }
>>> +# CHECK: - { id: 1, class: gprb }
>>> +# CHECK: - { id: 2, class: fprb }
>>> +# CHECK: - { id: 3, class: gprb }
>>> +# CHECK: - { id: 4, class: gprb }
>>> +
>>> +registers:
>>> +  - { id: 0, class: _ }
>>> +  - { id: 1, class: _ }
>>> +  - { id: 2, class: _ }
>>> +  - { id: 3, class: _ }
>>> +  - { id: 4, class: _ }
>>> +body:             |
>>> +  bb.0:
>>> +    liveins: %r0, %r1
>>> +
>>> +    %0(s32) = COPY %r0
>>> +    %1(s32) = COPY %r1
>>> +    %2(s64) = G_SEQUENCE %0(s32), 0, %1(s32), 32
>>> +    %3(s32), %4(s32) = G_EXTRACT %2(s64), 0, 32
>>> +    %r0 = COPY %3(s32)
>>> +    %r1 = COPY %4(s32)
>>> +    BX_RET 14, _, implicit %r0, implicit %r1
>>>
>>> ...
>>>
>>>
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