[PATCH] D30021: [LSR] Prevent formula with SCEVAddRecExpr type of Reg from Sibling loops
Wei Mi via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Thu Feb 16 13:39:06 PST 2017
This revision was automatically updated to reflect the committed changes.
Closed by commit rL295378: [LSR] Prevent formula with SCEVAddRecExpr type of Reg from Sibling loops (authored by wmi).
Changed prior to commit:
https://reviews.llvm.org/D30021?vs=88637&id=88775#toc
Repository:
rL LLVM
https://reviews.llvm.org/D30021
Files:
llvm/trunk/lib/Transforms/Scalar/LoopStrengthReduce.cpp
llvm/trunk/test/Transforms/LoopStrengthReduce/X86/sibling-loops.ll
-------------- next part --------------
A non-text attachment was scrubbed...
Name: D30021.88775.patch
Type: text/x-patch
Size: 4916 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20170216/f0cdbe6d/attachment.bin>
More information about the llvm-commits
mailing list