[llvm] r295027 - [RISCV] Pseudo instructions are isCodeGenOnly, have blank asmstr

Alex Bradbury via llvm-commits llvm-commits at lists.llvm.org
Mon Feb 13 21:17:23 PST 2017


Author: asb
Date: Mon Feb 13 23:17:23 2017
New Revision: 295027

URL: http://llvm.org/viewvc/llvm-project?rev=295027&view=rev
Log:
[RISCV] Pseudo instructions are isCodeGenOnly, have blank asmstr

Modified:
    llvm/trunk/lib/Target/RISCV/RISCVInstrFormats.td

Modified: llvm/trunk/lib/Target/RISCV/RISCVInstrFormats.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/RISCV/RISCVInstrFormats.td?rev=295027&r1=295026&r2=295027&view=diff
==============================================================================
--- llvm/trunk/lib/Target/RISCV/RISCVInstrFormats.td (original)
+++ llvm/trunk/lib/Target/RISCV/RISCVInstrFormats.td Mon Feb 13 23:17:23 2017
@@ -44,8 +44,9 @@ class RISCVInst<dag outs, dag ins, strin
 
 // Pseudo instructions
 class Pseudo<dag outs, dag ins, string asmstr, list<dag> pattern>
-    : RISCVInst<outs, ins, asmstr, pattern> {
+    : RISCVInst<outs, ins, "", pattern> {
   let isPseudo = 1;
+  let isCodeGenOnly = 1;
 }
 
 class FR<bits<7> funct7, bits<3> funct3, bits<7> opcode, dag outs, dag ins,




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