[PATCH] D29385: Clzero intrinsic and its addition under znver1

[Andrea Di Biagio via Phabricator via llvm-commits]

andreadb added a comment.

I have a (probably dumb) question: should CLZERO be treated as a memory read/write barrier for the purpose of scheduling? Is it okay to reoder CLFLUSH based on the EAX/RAX register dependency only?

I am asking this because it looks to me that we don't model the 'flush/zero' behavior of cache line operations on x86. For what I can see (please correct me if I am wrong), nothing in the code suggests that CLZERO (or even CLFLUSH) is treated as a memory barrier for scheduling purpose. Is that behavior intended (i.e. do we care about it)? Am I reading those tablegen definitions incorrectly?


Repository:
  rL LLVM

https://reviews.llvm.org/D29385