[PATCH] D29446: [AArch64] Fix incorrect MachinePointerInfo in splitStoreSplat

[John Brawn via Phabricator via llvm-commits]

john.brawn added inline comments.


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Comment at: test/CodeGen/AArch64/ldst-zero.ll:13
+; CHECK: stp xzr, xzr, [x0, #8]
+; CHECK: stp xzr, x2, [x0]
+; CHECK: str w1, [x0, #16]
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gberry wrote:
> These first two checks can be CHECK-DAG since they can be scheduled independently.  The same applies to all of these tests I believe.
Actually they can't be scheduled independently, they both write to x0+8 (the first writes xzr, the second writes x2).


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Comment at: test/CodeGen/AArch64/misched-stp.ll:10
+; CHECK: test_splat:BB#0 entry
+; CHECK: SU(4):   STRWui %vreg3, %vreg2, 3; mem:ST4[%3+8] GPR32:%vreg3 GPR64common:%vreg2
+; CHECK: Successors:
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gberry wrote:
> You might want to make the %vreg matching a little less brittle (i.e. match %vreg{{[0-9]+}} instead of %vreg3 since you aren't really checking anything related to the registers).  The same probably goes for the Latency, which can probably just be dropped entirely.  And the SU numbers.
Sounds like a good idea, I'll do that.


Repository:
  rL LLVM

https://reviews.llvm.org/D29446