ISD::ZERO_EXTEND / SIGN_EXTEND of sub-vectors

[Friedman, Eli via llvm-commits]

On 1/24/2017 11:09 PM, Jonas Paulsson wrote:
> Hi Eli,
>
>
>> Are you sure "InOp" is the right input to the operation? 
>> SIGN_EXTEND_VECTOR_INREG expects that the input and the output are 
>> the same size, but you aren't doing anything to ensure that.
>>
>>
> I was expecting GetWidenedVector() which always returns a widened 
> vector, to return a vector of legal width. But I guess it can't hurt 
> to verify that this is the case. Please see attached updated patch. 

Just because the input and output have legal width, doesn't necessarily 
mean that they have the same width... many targets support multiple 
vector widths.

+    if (WidenVT.getSizeInBits() == InVT.getSizeInBits()){

Whitespace.  Could also use a comment describing what sort of input/output types you expect to handle here.

Needs testcases.

-Eli

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