[PATCH] D28626: RFC: Generalize inverted gc dependencies
Rafael Espíndola via llvm-commits
llvm-commits at lists.llvm.org
Tue Jan 24 13:25:45 PST 2017
So, it is not completely clear what the xmos assembler and linker use.
This patch just completely deletes the flags and leaves just the
section names.
Robert, is that what is used? If not, what are the 'c' and 'd' in
section ...,"awc", at progbits
section ...,"awd", at progbits
mapped to by the assembler?
Cheers,
Rafael
On 24 January 2017 at 14:49, Rafael Avila de Espindola
<rafael.espindola at gmail.com> wrote:
> Robert Lytton <robert at xmos.com> writes:
>
>> yes, sorry, I realised that on the way home!
>> No, we don't - they are opaque.
>> Please do refactor appropriately - thank you.
>
> Awesome. Can you share how they are represented in the .o file? I may as
> well change MC to represent them in the same way your assembler does.
>
> Cheers,
> Rafael
-------------- next part --------------
diff --git a/llvm/include/llvm/Support/ELF.h b/llvm/include/llvm/Support/ELF.h
index 3ea4da8..3da4fd8 100644
--- a/llvm/include/llvm/Support/ELF.h
+++ b/llvm/include/llvm/Support/ELF.h
@@ -750,17 +750,6 @@ enum : unsigned {
SHF_EXCLUDE = 0x80000000U,
// Start of target-specific flags.
-
- /// XCORE_SHF_CP_SECTION - All sections with the "c" flag are grouped
- /// together by the linker to form the constant pool and the cp register is
- /// set to the start of the constant pool by the boot code.
- XCORE_SHF_CP_SECTION = 0x800U,
-
- /// XCORE_SHF_DP_SECTION - All sections with the "d" flag are grouped
- /// together by the linker to form the data section and the dp register is
- /// set to the start of the section by the boot code.
- XCORE_SHF_DP_SECTION = 0x1000U,
-
SHF_MASKOS = 0x0ff00000,
// Bits indicating processor-specific flags.
diff --git a/llvm/lib/MC/MCParser/ELFAsmParser.cpp b/llvm/lib/MC/MCParser/ELFAsmParser.cpp
index 8d7ba0d..1fcc26a 100644
--- a/llvm/lib/MC/MCParser/ELFAsmParser.cpp
+++ b/llvm/lib/MC/MCParser/ELFAsmParser.cpp
@@ -291,12 +291,6 @@ static unsigned parseSectionFlags(StringRef flagsStr, bool *UseLastGroup) {
case 'T':
flags |= ELF::SHF_TLS;
break;
- case 'c':
- flags |= ELF::XCORE_SHF_CP_SECTION;
- break;
- case 'd':
- flags |= ELF::XCORE_SHF_DP_SECTION;
- break;
case 'y':
flags |= ELF::SHF_ARM_PURECODE;
break;
diff --git a/llvm/lib/MC/MCSectionELF.cpp b/llvm/lib/MC/MCSectionELF.cpp
index 587b28f..561ff87 100644
--- a/llvm/lib/MC/MCSectionELF.cpp
+++ b/llvm/lib/MC/MCSectionELF.cpp
@@ -106,10 +106,6 @@ void MCSectionELF::PrintSwitchToSection(const MCAsmInfo &MAI,
OS << 'T';
// If there are target-specific flags, print them.
- if (Flags & ELF::XCORE_SHF_CP_SECTION)
- OS << 'c';
- if (Flags & ELF::XCORE_SHF_DP_SECTION)
- OS << 'd';
if (Flags & ELF::SHF_ARM_PURECODE)
OS << 'y';
diff --git a/llvm/lib/Target/XCore/XCoreTargetObjectFile.cpp b/llvm/lib/Target/XCore/XCoreTargetObjectFile.cpp
index ad8693f..427a102 100644
--- a/llvm/lib/Target/XCore/XCoreTargetObjectFile.cpp
+++ b/llvm/lib/Target/XCore/XCoreTargetObjectFile.cpp
@@ -22,42 +22,36 @@ void XCoreTargetObjectFile::Initialize(MCContext &Ctx, const TargetMachine &TM){
TargetLoweringObjectFileELF::Initialize(Ctx, TM);
BSSSection = Ctx.getELFSection(".dp.bss", ELF::SHT_NOBITS,
- ELF::SHF_ALLOC | ELF::SHF_WRITE |
- ELF::XCORE_SHF_DP_SECTION);
+ ELF::SHF_ALLOC | ELF::SHF_WRITE);
BSSSectionLarge = Ctx.getELFSection(".dp.bss.large", ELF::SHT_NOBITS,
- ELF::SHF_ALLOC | ELF::SHF_WRITE |
- ELF::XCORE_SHF_DP_SECTION);
+ ELF::SHF_ALLOC | ELF::SHF_WRITE);
DataSection = Ctx.getELFSection(".dp.data", ELF::SHT_PROGBITS,
- ELF::SHF_ALLOC | ELF::SHF_WRITE |
- ELF::XCORE_SHF_DP_SECTION);
+ ELF::SHF_ALLOC | ELF::SHF_WRITE);
DataSectionLarge = Ctx.getELFSection(".dp.data.large", ELF::SHT_PROGBITS,
- ELF::SHF_ALLOC | ELF::SHF_WRITE |
- ELF::XCORE_SHF_DP_SECTION);
+ ELF::SHF_ALLOC | ELF::SHF_WRITE);
DataRelROSection = Ctx.getELFSection(".dp.rodata", ELF::SHT_PROGBITS,
- ELF::SHF_ALLOC | ELF::SHF_WRITE |
- ELF::XCORE_SHF_DP_SECTION);
+ ELF::SHF_ALLOC | ELF::SHF_WRITE);
DataRelROSectionLarge = Ctx.getELFSection(
".dp.rodata.large", ELF::SHT_PROGBITS,
- ELF::SHF_ALLOC | ELF::SHF_WRITE | ELF::XCORE_SHF_DP_SECTION);
+ ELF::SHF_ALLOC | ELF::SHF_WRITE);
ReadOnlySection =
Ctx.getELFSection(".cp.rodata", ELF::SHT_PROGBITS,
- ELF::SHF_ALLOC | ELF::XCORE_SHF_CP_SECTION);
+ ELF::SHF_ALLOC);
ReadOnlySectionLarge =
Ctx.getELFSection(".cp.rodata.large", ELF::SHT_PROGBITS,
- ELF::SHF_ALLOC | ELF::XCORE_SHF_CP_SECTION);
+ ELF::SHF_ALLOC);
MergeableConst4Section = Ctx.getELFSection(
".cp.rodata.cst4", ELF::SHT_PROGBITS,
- ELF::SHF_ALLOC | ELF::SHF_MERGE | ELF::XCORE_SHF_CP_SECTION, 4, "");
+ ELF::SHF_ALLOC | ELF::SHF_MERGE, 4, "");
MergeableConst8Section = Ctx.getELFSection(
".cp.rodata.cst8", ELF::SHT_PROGBITS,
- ELF::SHF_ALLOC | ELF::SHF_MERGE | ELF::XCORE_SHF_CP_SECTION, 8, "");
+ ELF::SHF_ALLOC | ELF::SHF_MERGE, 8, "");
MergeableConst16Section = Ctx.getELFSection(
".cp.rodata.cst16", ELF::SHT_PROGBITS,
- ELF::SHF_ALLOC | ELF::SHF_MERGE | ELF::XCORE_SHF_CP_SECTION, 16, "");
+ ELF::SHF_ALLOC | ELF::SHF_MERGE, 16, "");
CStringSection =
Ctx.getELFSection(".cp.rodata.string", ELF::SHT_PROGBITS,
- ELF::SHF_ALLOC | ELF::SHF_MERGE | ELF::SHF_STRINGS |
- ELF::XCORE_SHF_CP_SECTION);
+ ELF::SHF_ALLOC | ELF::SHF_MERGE | ELF::SHF_STRINGS);
// TextSection - see MObjectFileInfo.cpp
// StaticCtorSection - see MObjectFileInfo.cpp
// StaticDtorSection - see MObjectFileInfo.cpp
@@ -77,10 +71,6 @@ static unsigned getXCoreSectionFlags(SectionKind K, bool IsCPRel) {
if (K.isText())
Flags |= ELF::SHF_EXECINSTR;
- else if (IsCPRel)
- Flags |= ELF::XCORE_SHF_CP_SECTION;
- else
- Flags |= ELF::XCORE_SHF_DP_SECTION;
if (K.isWriteable())
Flags |= ELF::SHF_WRITE;
diff --git a/llvm/test/CodeGen/XCore/codemodel.ll b/llvm/test/CodeGen/XCore/codemodel.ll
index 4e63799..bd01ca1 100644
--- a/llvm/test/CodeGen/XCore/codemodel.ll
+++ b/llvm/test/CodeGen/XCore/codemodel.ll
@@ -36,7 +36,7 @@ entry:
}
-; CHECK: .section .cp.rodata.cst4,"aMc", at progbits,4
+; CHECK: .section .cp.rodata.cst4,"aM", at progbits,4
; CHECK: .long 65536
; CHECK: .text
; CHECK-LABEL: f:
@@ -61,9 +61,9 @@ entry:
; CHECK: add r0, r0, r1
; CHECK: retsp 0
;
-; LARGE: .section .cp.rodata.cst4,"aMc", at progbits,4
+; LARGE: .section .cp.rodata.cst4,"aM", at progbits,4
; LARGE: .long 65536
-; LARGE: .section .cp.rodata,"ac", at progbits
+; LARGE: .section .cp.rodata,"a", at progbits
; LARGE: .long l
; LARGE: .long l+4
; LARGE: .long l+392
@@ -121,7 +121,7 @@ entry:
; CHECK: ldw r0, dp[NoSize+40]
; CHECK-NEXT: retsp 0
;
-; LARGE: .section .cp.rodata,"ac", at progbits
+; LARGE: .section .cp.rodata,"a", at progbits
; LARGE: .LCPI{{[0-9_]*}}
; LARGE-NEXT: .long NoSize
; LARGE-NEXT: .text
@@ -141,7 +141,7 @@ entry:
; CHECK: ldaw r0, dp[Unknown]
; CHECK-NEXT: retsp 0
;
-; LARGE: .section .cp.rodata,"ac", at progbits
+; LARGE: .section .cp.rodata,"a", at progbits
; LARGE: .LCPI{{[0-9_]*}}
; LARGE-NEXT: .long Unknown
; LARGE-NEXT: .text
@@ -156,57 +156,57 @@ entry:
}
-; CHECK: .section .dp.bss,"awd", at nobits
+; CHECK: .section .dp.bss,"aw", at nobits
; CHECK-LABEL: l:
; CHECK: .space 400
-; LARGE: .section .dp.bss.large,"awd", at nobits
+; LARGE: .section .dp.bss.large,"aw", at nobits
; LARGE-LABEL: l:
; LARGE: .space 400
@l = global [100 x i32] zeroinitializer
; CHECK-LABEL: s:
; CHECK: .space 40
-; LARGE: .section .dp.bss,"awd", at nobits
+; LARGE: .section .dp.bss,"aw", at nobits
; LARGE-LABEL: s:
; LARGE: .space 40
@s = global [10 x i32] zeroinitializer
-; CHECK: .section .dp.rodata,"awd", at progbits
+; CHECK: .section .dp.rodata,"aw", at progbits
; CHECK-LABEL: cl:
; CHECK: .space 400
-; LARGE: .section .dp.rodata.large,"awd", at progbits
+; LARGE: .section .dp.rodata.large,"aw", at progbits
; LARGE-LABEL: cl:
; LARGE: .space 400
@cl = constant [100 x i32] zeroinitializer
; CHECK-LABEL: cs:
; CHECK: .space 40
-; LARGE: .section .dp.rodata,"awd", at progbits
+; LARGE: .section .dp.rodata,"aw", at progbits
; LARGE-LABEL: cs:
; LARGE: .space 40
@cs = constant [10 x i32] zeroinitializer
-; CHECK: .section .cp.rodata,"ac", at progbits
+; CHECK: .section .cp.rodata,"a", at progbits
; CHECK-LABEL: icl:
; CHECK: .space 400
-; LARGE: .section .cp.rodata.large,"ac", at progbits
+; LARGE: .section .cp.rodata.large,"a", at progbits
; LARGE-LABEL: icl:
; LARGE: .space 400
@icl = internal constant [100 x i32] zeroinitializer
; CHECK-LABEL: cs:
; CHECK: .space 40
-; LARGE: .section .cp.rodata,"ac", at progbits
+; LARGE: .section .cp.rodata,"a", at progbits
; LARGE-LABEL: cs:
; LARGE: .space 40
@ics = internal constant [10 x i32] zeroinitializer
-; CHECK: .section .cp.namedsection,"ac", at progbits
+; CHECK: .section .cp.namedsection,"a", at progbits
; CHECK-LABEL: cpsec:
; CHECK: .long 0
@cpsec = constant i32 0, section ".cp.namedsection"
-; CHECK: .section .dp.namedsection,"awd", at progbits
+; CHECK: .section .dp.namedsection,"aw", at progbits
; CHECK-LABEL: dpsec:
; CHECK: .long 0
@dpsec = global i32 0, section ".dp.namedsection"
diff --git a/llvm/test/CodeGen/XCore/constants.ll b/llvm/test/CodeGen/XCore/constants.ll
index c289bf9..0837b4a 100644
--- a/llvm/test/CodeGen/XCore/constants.ll
+++ b/llvm/test/CodeGen/XCore/constants.ll
@@ -1,6 +1,6 @@
; RUN: llc < %s -march=xcore -mcpu=xs1b-generic | FileCheck %s
-; CHECK: .section .cp.rodata.cst4,"aMc", at progbits,4
+; CHECK: .section .cp.rodata.cst4,"aM", at progbits,4
; CHECK: .LCPI0_0:
; CHECK: .long 12345678
; CHECK-LABEL: f:
diff --git a/llvm/test/CodeGen/XCore/epilogue_prologue.ll b/llvm/test/CodeGen/XCore/epilogue_prologue.ll
index aed49f4..731119e 100644
--- a/llvm/test/CodeGen/XCore/epilogue_prologue.ll
+++ b/llvm/test/CodeGen/XCore/epilogue_prologue.ll
@@ -100,7 +100,7 @@ entry:
; FP + large frame: spill FP+SR+R4+LR = entsp 3 + 200000 + extsp 1
-; CHECKFP: .section .cp.rodata.cst4,"aMc", at progbits,4
+; CHECKFP: .section .cp.rodata.cst4,"aM", at progbits,4
; CHECKFP-NEXT: .p2align 2
; CHECKFP-NEXT: .LCPI[[CNST0:[0-9_]+]]:
; CHECKFP-NEXT: .long 200002
@@ -153,7 +153,7 @@ entry:
; CHECKFP-NEXT: retsp 3398
;
; !FP + large frame: spill SR+SR+R4+LR = entsp 4 + 200000
-; CHECK: .section .cp.rodata.cst4,"aMc", at progbits,4
+; CHECK: .section .cp.rodata.cst4,"aM", at progbits,4
; CHECK-NEXT: .p2align 2
; CHECK-NEXT: .LCPI[[CNST0:[0-9_]+]]:
; CHECK-NEXT: .long 200003
diff --git a/llvm/test/CodeGen/XCore/globals.ll b/llvm/test/CodeGen/XCore/globals.ll
index 04e135c..ac594a7 100644
--- a/llvm/test/CodeGen/XCore/globals.ll
+++ b/llvm/test/CodeGen/XCore/globals.ll
@@ -81,47 +81,47 @@ entry:
}
@G1 = global i32 4712
-; CHECK: .section .dp.data,"awd", at progbits
+; CHECK: .section .dp.data,"aw", at progbits
; CHECK: G1:
@G2 = global i32 0
-; CHECK: .section .dp.bss,"awd", at nobits
+; CHECK: .section .dp.bss,"aw", at nobits
; CHECK: G2:
@G3 = unnamed_addr constant i32 9401
-; CHECK: .section .dp.rodata,"awd", at progbits
+; CHECK: .section .dp.rodata,"aw", at progbits
; CHECK: G3:
@iG3 = internal constant i32 9401
-; CHECK: .section .cp.rodata,"ac", at progbits
+; CHECK: .section .cp.rodata,"a", at progbits
; CHECK: iG3:
@G4 = global i32* @G1
-; CHECK: .section .dp.data,"awd", at progbits
+; CHECK: .section .dp.data,"aw", at progbits
; CHECK: G4:
@G5 = unnamed_addr constant i32* @G1
-; CHECK: .section .dp.rodata,"awd", at progbits
+; CHECK: .section .dp.rodata,"aw", at progbits
; CHECK: G5:
@iG5 = internal unnamed_addr constant i32* @G1
-; CHECK: .section .cp.rodata,"ac", at progbits
+; CHECK: .section .cp.rodata,"a", at progbits
; CHECK: iG5:
@G6 = global i32* @G8
-; CHECK: .section .dp.data,"awd", at progbits
+; CHECK: .section .dp.data,"aw", at progbits
; CHECK: G6:
@G7 = unnamed_addr constant i32* @G8
-; CHECK: .section .dp.rodata,"awd", at progbits
+; CHECK: .section .dp.rodata,"aw", at progbits
; CHECK: G7:
@iG7 = internal unnamed_addr constant i32* @G8
-; CHECK: .section .cp.rodata,"ac", at progbits
+; CHECK: .section .cp.rodata,"a", at progbits
; CHECK: iG7:
@G8 = global i32 9312
-; CHECK: .section .dp.data,"awd", at progbits
+; CHECK: .section .dp.data,"aw", at progbits
; CHECK: G8:
@array = global [10 x i16] zeroinitializer, align 2
diff --git a/llvm/test/CodeGen/XCore/scavenging.ll b/llvm/test/CodeGen/XCore/scavenging.ll
index b46c75a..3b7f3be 100644
--- a/llvm/test/CodeGen/XCore/scavenging.ll
+++ b/llvm/test/CodeGen/XCore/scavenging.ll
@@ -52,7 +52,7 @@ entry:
declare void @g(i32*, i32*)
-; CHECK: .section .cp.rodata.cst4,"aMc", at progbits,4
+; CHECK: .section .cp.rodata.cst4,"aM", at progbits,4
; CHECK: .p2align 2
; CHECK: [[ARG5:.LCPI[0-9_]+]]:
; CHECK: .long 100003
diff --git a/llvm/test/CodeGen/XCore/tls.ll b/llvm/test/CodeGen/XCore/tls.ll
index 648d611..96e512a 100644
--- a/llvm/test/CodeGen/XCore/tls.ll
+++ b/llvm/test/CodeGen/XCore/tls.ll
@@ -8,7 +8,7 @@ entry:
}
@G = thread_local global i32 15
-; CHECK: .section .dp.data,"awd", at progbits
+; CHECK: .section .dp.data,"aw", at progbits
; CHECK: G:
; CHECK: .long 15
; CHECK: .long 15
diff --git a/llvm/tools/llvm-readobj/ELFDumper.cpp b/llvm/tools/llvm-readobj/ELFDumper.cpp
index 0a3cd7a..55fe0d5 100644
--- a/llvm/tools/llvm-readobj/ELFDumper.cpp
+++ b/llvm/tools/llvm-readobj/ELFDumper.cpp
@@ -1057,11 +1057,6 @@ static const EnumEntry<unsigned> ElfSectionFlags[] = {
ENUM_ENT_1(SHF_COMPRESSED),
};
-static const EnumEntry<unsigned> ElfXCoreSectionFlags[] = {
- LLVM_READOBJ_ENUM_ENT(ELF, XCORE_SHF_CP_SECTION),
- LLVM_READOBJ_ENUM_ENT(ELF, XCORE_SHF_DP_SECTION)
-};
-
static const EnumEntry<unsigned> ElfAMDGPUSectionFlags[] = {
LLVM_READOBJ_ENUM_ENT(ELF, SHF_AMDGPU_HSA_GLOBAL),
LLVM_READOBJ_ENUM_ENT(ELF, SHF_AMDGPU_HSA_READONLY),
@@ -3628,10 +3623,6 @@ template <class ELFT> void LLVMStyle<ELFT>::printSections(const ELFO *Obj) {
SectionFlags.insert(SectionFlags.end(), std::begin(ElfX86_64SectionFlags),
std::end(ElfX86_64SectionFlags));
break;
- case EM_XCORE:
- SectionFlags.insert(SectionFlags.end(), std::begin(ElfXCoreSectionFlags),
- std::end(ElfXCoreSectionFlags));
- break;
default:
// Nothing to do.
break;
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