[PATCH] D28922: [LoadCombine] Fix combining of loads which span an aliasing store.

[Michael Spencer via Phabricator via llvm-commits]

Bigcheese created this revision.

Fixes PR31517

I'm not 100% sure about this fix. The problem is we don't check if the last load aliases anything, so this now checks all instructions to see if they alias and adds stores to the alias set. However I'm not sure if memcpy/memset or any other ways of writing need to be handled specially here.


Repository:
  rL LLVM

https://reviews.llvm.org/D28922

Files:
  lib/Transforms/Scalar/LoadCombine.cpp
  test/Transforms/LoadCombine/load-combine-aa.ll


Index: test/Transforms/LoadCombine/load-combine-aa.ll
===================================================================
--- test/Transforms/LoadCombine/load-combine-aa.ll
+++ test/Transforms/LoadCombine/load-combine-aa.ll
@@ -37,3 +37,24 @@
   ret i64 %add
 }
 
+%rec11 = type { i16, i16, i16 }
+ at str = global %rec11 { i16 1, i16 2, i16 3 }
+
+; PR31517 - Check that loads which span an aliasing store are not combined.
+define i16 @test3() {
+; CHECK-LABEL: @test3
+
+; CHECK: load i16, i16*
+; CHECK: store i16
+; CHECK: ret i16
+
+  %_tmp9 = getelementptr %rec11, %rec11* @str, i16 0, i32 1
+  %_tmp10 = load i16, i16* %_tmp9
+  %_tmp12 = getelementptr %rec11, %rec11* @str, i16 0, i32 0
+  store i16 %_tmp10, i16* %_tmp12
+  %_tmp13 = getelementptr %rec11, %rec11* @str, i16 0, i32 0
+  %_tmp14 = load i16, i16* %_tmp13
+  %_tmp15 = icmp eq i16 %_tmp14, 3
+  %_tmp16 = select i1 %_tmp15, i16 1, i16 0
+  ret i16 %_tmp16
+}
Index: lib/Transforms/Scalar/LoadCombine.cpp
===================================================================
--- lib/Transforms/Scalar/LoadCombine.cpp
+++ lib/Transforms/Scalar/LoadCombine.cpp
@@ -245,13 +245,17 @@
   bool Combined = false;
   unsigned Index = 0;
   for (auto &I : BB) {
-    if (I.mayThrow() || (I.mayWriteToMemory() && AST.containsUnknown(&I))) {
+    if (I.mayThrow() || AST.containsUnknown(&I)) {
       if (combineLoads(LoadMap))
         Combined = true;
       LoadMap.clear();
       AST.clear();
       continue;
     }
+    if (StoreInst *SI = dyn_cast<StoreInst>(&I)) {
+      AST.add(SI);
+      continue;
+    }
     LoadInst *LI = dyn_cast<LoadInst>(&I);
     if (!LI)
       continue;


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