[PATCH] D28556: [CodeGen] Rename MachineInstrBuilder::addOperand

[Diana Picus via Phabricator via llvm-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rL291891: [CodeGen] Rename MachineInstrBuilder::addOperand. NFC (authored by rovka).

Changed prior to commit:
  https://reviews.llvm.org/D28556?vs=83958&id=84261#toc

Repository:
  rL LLVM

https://reviews.llvm.org/D28556

Files:
  llvm/trunk/include/llvm/CodeGen/MachineInstrBuilder.h
  llvm/trunk/lib/CodeGen/ImplicitNullChecks.cpp
  llvm/trunk/lib/CodeGen/LiveDebugVariables.cpp
  llvm/trunk/lib/CodeGen/PatchableFunction.cpp
  llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp
  llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
  llvm/trunk/lib/CodeGen/TargetInstrInfo.cpp
  llvm/trunk/lib/CodeGen/TargetLoweringBase.cpp
  llvm/trunk/lib/CodeGen/TwoAddressInstructionPass.cpp
  llvm/trunk/lib/CodeGen/XRayInstrumentation.cpp
  llvm/trunk/lib/Target/AArch64/AArch64CallLowering.cpp
  llvm/trunk/lib/Target/AArch64/AArch64ConditionOptimizer.cpp
  llvm/trunk/lib/Target/AArch64/AArch64ConditionalCompares.cpp
  llvm/trunk/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp
  llvm/trunk/lib/Target/AArch64/AArch64FrameLowering.cpp
  llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.cpp
  llvm/trunk/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp
  llvm/trunk/lib/Target/AMDGPU/R600ISelLowering.cpp
  llvm/trunk/lib/Target/AMDGPU/SIFixSGPRCopies.cpp
  llvm/trunk/lib/Target/AMDGPU/SIISelLowering.cpp
  llvm/trunk/lib/Target/AMDGPU/SIInsertSkips.cpp
  llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.cpp
  llvm/trunk/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp
  llvm/trunk/lib/Target/AMDGPU/SILowerControlFlow.cpp
  llvm/trunk/lib/Target/AMDGPU/SILowerI1Copies.cpp
  llvm/trunk/lib/Target/AMDGPU/SIRegisterInfo.cpp
  llvm/trunk/lib/Target/AMDGPU/SIShrinkInstructions.cpp
  llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp
  llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp
  llvm/trunk/lib/Target/ARM/ARMExpandPseudoInsts.cpp
  llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
  llvm/trunk/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
  llvm/trunk/lib/Target/ARM/Thumb1FrameLowering.cpp
  llvm/trunk/lib/Target/ARM/Thumb2SizeReduction.cpp
  llvm/trunk/lib/Target/AVR/AVRExpandPseudoInsts.cpp
  llvm/trunk/lib/Target/Hexagon/HexagonBitSimplify.cpp
  llvm/trunk/lib/Target/Hexagon/HexagonEarlyIfConv.cpp
  llvm/trunk/lib/Target/Hexagon/HexagonExpandCondsets.cpp
  llvm/trunk/lib/Target/Hexagon/HexagonFixupHwLoops.cpp
  llvm/trunk/lib/Target/Hexagon/HexagonFrameLowering.cpp
  llvm/trunk/lib/Target/Hexagon/HexagonGenMux.cpp
  llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.cpp
  llvm/trunk/lib/Target/Hexagon/HexagonOptAddrMode.cpp
  llvm/trunk/lib/Target/Lanai/LanaiInstrInfo.cpp
  llvm/trunk/lib/Target/MSP430/MSP430BranchSelector.cpp
  llvm/trunk/lib/Target/Mips/MipsInstrInfo.cpp
  llvm/trunk/lib/Target/Mips/MipsSEISelLowering.cpp
  llvm/trunk/lib/Target/NVPTX/NVPTXPeephole.cpp
  llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp
  llvm/trunk/lib/Target/PowerPC/PPCMIPeephole.cpp
  llvm/trunk/lib/Target/PowerPC/PPCVSXCopy.cpp
  llvm/trunk/lib/Target/PowerPC/PPCVSXSwapRemoval.cpp
  llvm/trunk/lib/Target/SystemZ/SystemZElimCompare.cpp
  llvm/trunk/lib/Target/SystemZ/SystemZISelLowering.cpp
  llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.cpp
  llvm/trunk/lib/Target/SystemZ/SystemZLongBranch.cpp
  llvm/trunk/lib/Target/SystemZ/SystemZShortenInst.cpp
  llvm/trunk/lib/Target/WebAssembly/WebAssemblyInstrInfo.cpp
  llvm/trunk/lib/Target/WebAssembly/WebAssemblyLowerBrUnless.cpp
  llvm/trunk/lib/Target/X86/X86CallFrameOptimization.cpp
  llvm/trunk/lib/Target/X86/X86ExpandPseudo.cpp
  llvm/trunk/lib/Target/X86/X86FixupBWInsts.cpp
  llvm/trunk/lib/Target/X86/X86FixupLEAs.cpp
  llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
  llvm/trunk/lib/Target/X86/X86InstrBuilder.h
  llvm/trunk/lib/Target/X86/X86InstrInfo.cpp

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