[PATCH] D28522: Codegen: Make chains from lattice-shaped CFGs

Tue Jan 10 11:39:27 PST 2017

iteratee created this revision.
iteratee added a reviewer: davidxl.
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This change extends https://reviews.llvm.org/D27742 to allow a chain of triangles to
tail-duplicate and produce a lattice. The essential change is that if a
predecessor has the same successors as a layout predecessors, we ignore
that block when considering if we can tail-duplicate into unplaced
predecessors.

As an example consider the following CFG:

    B   D   F   H
   / \ / \ / \ / \
  A---C---E---G---Ret

Where A,C,E,G are all small (Currently 2 instructions).

The CFG preserving layout is then A,B,C,D,E,F,G,H,Ret.

The current code will copy C into B, E into D and G into F and yield the layout
A,C,B(C),E,D(E),F(G),G,H,ret

define void @straight_test(i32 %tag) {
entry:

  br label %test1

test1: ; A

  %tagbit1 = and i32 %tag, 1
  %tagbit1eq0 = icmp eq i32 %tagbit1, 0
  br i1 %tagbit1eq0, label %test2, label %optional1

optional1: ; B

  call void @a()
  br label %test2

test2: ; C

  %tagbit2 = and i32 %tag, 2
  %tagbit2eq0 = icmp eq i32 %tagbit2, 0
  br i1 %tagbit2eq0, label %test3, label %optional2

optional2: ; D

  call void @b()
  br label %test3

test3: ; E

  %tagbit3 = and i32 %tag, 4
  %tagbit3eq0 = icmp eq i32 %tagbit3, 0
  br i1 %tagbit3eq0, label %test4, label %optional3

optional3: ; F

  call void @c()
  br label %test4

test4: ; G

  %tagbit4 = and i32 %tag, 8
  %tagbit4eq0 = icmp eq i32 %tagbit4, 0
  br i1 %tagbit4eq0, label %exit, label %optional4

optional4: ; H

  call void @d()
  br label %exit

exit:

  ret void

}

here is the layout after https://reviews.llvm.org/D27742:
straight_test:                          # @straight_test
; ... Prologue elided
; BB#0:                                 # %entry ; A (merged with test1)
; ... More prologue elided

  mr 30, 3
  andi. 3, 30, 1
  bc 12, 1, .LBB0_2

; BB#1:                                 # %test2 ; C

  rlwinm. 3, 30, 0, 30, 30
  beq      0, .LBB0_3
  b .LBB0_4

.LBB0_2:                                # %optional1 ; B (copy of C)

  bl a
  nop
  rlwinm. 3, 30, 0, 30, 30
  bne      0, .LBB0_4

.LBB0_3:                                # %test3 ; E

  rlwinm. 3, 30, 0, 29, 29
  beq      0, .LBB0_5
  b .LBB0_6

.LBB0_4:                                # %optional2 ; D (copy of E)

  bl b
  nop
  rlwinm. 3, 30, 0, 29, 29
  bne      0, .LBB0_6

.LBB0_5:                                # %test4 ; G

  rlwinm. 3, 30, 0, 28, 28
  beq      0, .LBB0_8
  b .LBB0_7

.LBB0_6:                                # %optional3 ; F (copy of G)

  bl c
  nop
  rlwinm. 3, 30, 0, 28, 28
  beq      0, .LBB0_8

.LBB0_7:                                # %optional4 ; H

  bl d
  nop

.LBB0_8:                                # %exit ; Ret

  ld 30, 96(1)                    # 8-byte Folded Reload
  addi 1, 1, 112
  ld 0, 16(1)
  mtlr 0
  blr

This is where the more bold strategy of this patch comes in. We allow E
to be placed, even though its predecessor B (after copying C) is
unplaced, because it is lattice shaped after tail-duplication.
This then produces the layout A,C,E,G,B,D,F,H,Ret. This layout does have
back edges, which is a negative, but it has a bigger compensating
positive, which is that it handles the case where there are long strings
of skipped blocks much better than the original layout. Both layouts
handle runs of executed blocks equally well. Branch prediction also
improves if there is any correlation between subsequent optional blocks.

Here is the resulting concrete layout:

straight_test:                          # @straight_test
; BB#0:                                 # %entry ; A (merged with test1)

  mr 30, 3
  andi. 3, 30, 1
  bc 12, 1, .LBB0_4

; BB#1:                                 # %test2 ; C

  rlwinm. 3, 30, 0, 30, 30
  bne      0, .LBB0_5

.LBB0_2:                                # %test3 ; E

  rlwinm. 3, 30, 0, 29, 29
  bne      0, .LBB0_6

.LBB0_3:                                # %test4 ; G

  rlwinm. 3, 30, 0, 28, 28
  bne      0, .LBB0_7
  b .LBB0_8

.LBB0_4:                                # %optional1 ; B (Copy of C)

  bl a
  nop
  rlwinm. 3, 30, 0, 30, 30
  beq      0, .LBB0_2

.LBB0_5:                                # %optional2 ; D (Copy of E)

  bl b
  nop
  rlwinm. 3, 30, 0, 29, 29
  beq      0, .LBB0_3

.LBB0_6:                                # %optional3 ; F (Copy of G)

  bl c
  nop
  rlwinm. 3, 30, 0, 28, 28
  beq      0, .LBB0_8

.LBB0_7:                                # %optional4 ; H

  bl d
  nop

.LBB0_8:                                # %exit

Repository:
  rL LLVM

https://reviews.llvm.org/D28522

Files:
  lib/CodeGen/MachineBlockPlacement.cpp
  test/CodeGen/AArch64/branch-relax-cbz.ll
  test/CodeGen/AArch64/optimize-cond-branch.ll
  test/CodeGen/AMDGPU/basic-branch.ll
  test/CodeGen/AMDGPU/cf-loop-on-constant.ll
  test/CodeGen/AMDGPU/convergent-inlineasm.ll
  test/CodeGen/AMDGPU/salu-to-valu.ll
  test/CodeGen/AMDGPU/skip-if-dead.ll
  test/CodeGen/ARM/atomic-cmpxchg.ll
  test/CodeGen/ARM/fold-stack-adjust.ll
  test/CodeGen/PowerPC/tail-dup-layout.ll
  test/CodeGen/WebAssembly/mem-intrinsics.ll
  test/CodeGen/X86/block-placement.ll
  test/CodeGen/X86/tail-dup-merge-loop-headers.ll
  test/CodeGen/X86/tail-dup-repeat.ll
  test/CodeGen/X86/tail-opts.ll
  test/CodeGen/X86/twoaddr-coalesce-3.ll

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