[llvm] r291535 - [X86] When lowering uniform shifts, use X86ISD::VZEXT instead of using a ZERO_EXTEND_VECTOR_INREG. If we emit the ZERO_EXTEND_VECTOR_INREG too late it doesn't get lowered properly and makes it through to isel and fails.

[Andrea Di Biagio via llvm-commits]

Would it be possible to add a test case for it?

Thanks

On Tue, Jan 10, 2017 at 4:12 AM, Craig Topper via llvm-commits <
llvm-commits at lists.llvm.org> wrote:

> Author: ctopper
> Date: Mon Jan  9 22:12:24 2017
> New Revision: 291535
>
> URL: http://llvm.org/viewvc/llvm-project?rev=291535&view=rev
> Log:
> [X86] When lowering uniform shifts, use X86ISD::VZEXT instead of using a
> ZERO_EXTEND_VECTOR_INREG. If we emit the ZERO_EXTEND_VECTOR_INREG too late
> it doesn't get lowered properly and makes it through to isel and fails.
>
> Fixes PR31593.
>
> Modified:
>     llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
>
> Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/
> X86/X86ISelLowering.cpp?rev=291535&r1=291534&r2=291535&view=diff
> ============================================================
> ==================
> --- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
> +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Mon Jan  9 22:12:24 2017
> @@ -18418,13 +18418,13 @@ static SDValue getTargetVShiftNode(unsig
>      ShAmt = DAG.getNode(ISD::SCALAR_TO_VECTOR, SDLoc(ShAmt), MVT::v2i64,
> ShAmt);
>    else if (Subtarget.hasSSE41() && ShAmt.getOpcode() == ISD::ZERO_EXTEND
> &&
>             ShAmt.getOperand(0).getSimpleValueType() == MVT::i16) {
> -    SDValue Op0 = ShAmt.getOperand(0);
> -    Op0 = DAG.getNode(ISD::SCALAR_TO_VECTOR, SDLoc(Op0), MVT::v8i16,
> Op0);
> -    ShAmt = DAG.getZeroExtendVectorInReg(Op0, SDLoc(Op0), MVT::v2i64);
> +    ShAmt = ShAmt.getOperand(0);
> +    ShAmt = DAG.getNode(ISD::SCALAR_TO_VECTOR, SDLoc(ShAmt), MVT::v8i16,
> ShAmt);
> +    ShAmt = DAG.getNode(X86ISD::VZEXT, SDLoc(ShAmt), MVT::v2i64, ShAmt);
>    } else if (Subtarget.hasSSE41() &&
>               ShAmt.getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
>      ShAmt = DAG.getNode(ISD::SCALAR_TO_VECTOR, SDLoc(ShAmt), MVT::v4i32,
> ShAmt);
> -    ShAmt = DAG.getZeroExtendVectorInReg(ShAmt, SDLoc(ShAmt),
> MVT::v2i64);
> +    ShAmt = DAG.getNode(X86ISD::VZEXT, SDLoc(ShAmt), MVT::v2i64, ShAmt);
>    } else {
>      SmallVector<SDValue, 4> ShOps = {ShAmt, DAG.getConstant(0, dl, SVT),
>                                       DAG.getUNDEF(SVT),
> DAG.getUNDEF(SVT)};
>
>
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