<div dir="ltr"><div>Would it be possible to add a test case for it?<br></div><br>Thanks<br></div><div class="gmail_extra"><br><div class="gmail_quote">On Tue, Jan 10, 2017 at 4:12 AM, Craig Topper via llvm-commits <span dir="ltr"><<a href="mailto:llvm-commits@lists.llvm.org" target="_blank">llvm-commits@lists.llvm.org</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">Author: ctopper<br>
Date: Mon Jan  9 22:12:24 2017<br>
New Revision: 291535<br>
<br>
URL: <a href="http://llvm.org/viewvc/llvm-project?rev=291535&view=rev" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project?rev=291535&view=rev</a><br>
Log:<br>
[X86] When lowering uniform shifts, use X86ISD::VZEXT instead of using a ZERO_EXTEND_VECTOR_INREG. If we emit the ZERO_EXTEND_VECTOR_INREG too late it doesn't get lowered properly and makes it through to isel and fails.<br>
<br>
Fixes PR31593.<br>
<br>
Modified:<br>
    llvm/trunk/lib/Target/X86/<wbr>X86ISelLowering.cpp<br>
<br>
Modified: llvm/trunk/lib/Target/X86/<wbr>X86ISelLowering.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=291535&r1=291534&r2=291535&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/lib/Target/<wbr>X86/X86ISelLowering.cpp?rev=<wbr>291535&r1=291534&r2=291535&<wbr>view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/lib/Target/X86/<wbr>X86ISelLowering.cpp (original)<br>
+++ llvm/trunk/lib/Target/X86/<wbr>X86ISelLowering.cpp Mon Jan  9 22:12:24 2017<br>
@@ -18418,13 +18418,13 @@ static SDValue getTargetVShiftNode(unsig<br>
     ShAmt = DAG.getNode(ISD::SCALAR_TO_<wbr>VECTOR, SDLoc(ShAmt), MVT::v2i64, ShAmt);<br>
   else if (Subtarget.hasSSE41() && ShAmt.getOpcode() == ISD::ZERO_EXTEND &&<br>
            ShAmt.getOperand(0).<wbr>getSimpleValueType() == MVT::i16) {<br>
-    SDValue Op0 = ShAmt.getOperand(0);<br>
-    Op0 = DAG.getNode(ISD::SCALAR_TO_<wbr>VECTOR, SDLoc(Op0), MVT::v8i16, Op0);<br>
-    ShAmt = DAG.getZeroExtendVectorInReg(<wbr>Op0, SDLoc(Op0), MVT::v2i64);<br>
+    ShAmt = ShAmt.getOperand(0);<br>
+    ShAmt = DAG.getNode(ISD::SCALAR_TO_<wbr>VECTOR, SDLoc(ShAmt), MVT::v8i16, ShAmt);<br>
+    ShAmt = DAG.getNode(X86ISD::VZEXT, SDLoc(ShAmt), MVT::v2i64, ShAmt);<br>
   } else if (Subtarget.hasSSE41() &&<br>
              ShAmt.getOpcode() == ISD::EXTRACT_VECTOR_ELT) {<br>
     ShAmt = DAG.getNode(ISD::SCALAR_TO_<wbr>VECTOR, SDLoc(ShAmt), MVT::v4i32, ShAmt);<br>
-    ShAmt = DAG.getZeroExtendVectorInReg(<wbr>ShAmt, SDLoc(ShAmt), MVT::v2i64);<br>
+    ShAmt = DAG.getNode(X86ISD::VZEXT, SDLoc(ShAmt), MVT::v2i64, ShAmt);<br>
   } else {<br>
     SmallVector<SDValue, 4> ShOps = {ShAmt, DAG.getConstant(0, dl, SVT),<br>
                                      DAG.getUNDEF(SVT), DAG.getUNDEF(SVT)};<br>
<br>
<br>
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</blockquote></div><br></div>