[PATCH] D28194: [ARM] Classification Improvements to ARM Sched-Models. NFCI.

[Renato Golin via Phabricator via llvm-commits]

rengolin added a comment.

In https://reviews.llvm.org/D28194#637818, @javed.absar wrote:

> I tried not to club  too many of the sched-defs into one bucket because then sub-targets wouldn't be able to specify different latencies/resources if there was indeed a difference in the pipeline behavior for different instruction classes (e.g. between MUL32 and MUL64).


I see where you're coming from, but I'd rather have that differentiation done by the sub-architectures when they need, than just explode the combinations now, and having to apply larger patches every time one sub-arch needs one cost changed. :)

--renato


https://reviews.llvm.org/D28194