[PATCH] D28194: [ARM] Classification Improvements to ARM Sched-Models. NFCI.

[Javed Absar via Phabricator via llvm-commits]

javed.absar added a comment.

Hi Renato:

Thanks. OK, I will collapse the schedwrites into one wherever sub-targets, which currently have sched-model in place, do not differentiate.

I tried not to club  too many of the sched-defs into one bucket because then sub-targets wouldn't be able to specify different latencies/resources if there was indeed a difference in the pipeline behavior for different instruction classes (e.g. between MUL32 and MUL64). 
Best Regards, Javed.


https://reviews.llvm.org/D28194