[llvm] r290106 - [ARM] GlobalISel: Lower i8 and i16 register args
Diana Picus via llvm-commits
llvm-commits at lists.llvm.org
Mon Dec 19 06:08:02 PST 2016
Author: rovka
Date: Mon Dec 19 08:08:02 2016
New Revision: 290106
URL: http://llvm.org/viewvc/llvm-project?rev=290106&view=rev
Log:
[ARM] GlobalISel: Lower i8 and i16 register args
This allows lowering i8 and i16 arguments if they can fit in the registers. Note
that the lowering is incomplete - ABI extensions are handled in a subsequent
patch.
(Last part of)
Differential Revision: https://reviews.llvm.org/D27704
Modified:
llvm/trunk/lib/Target/ARM/ARMCallLowering.cpp
llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-irtranslator.ll
llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-isel.ll
Modified: llvm/trunk/lib/Target/ARM/ARMCallLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMCallLowering.cpp?rev=290106&r1=290105&r2=290106&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMCallLowering.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMCallLowering.cpp Mon Dec 19 08:08:02 2016
@@ -33,8 +33,11 @@ ARMCallLowering::ARMCallLowering(const A
static bool isSupportedType(const DataLayout DL, const ARMTargetLowering &TLI,
Type *T) {
EVT VT = TLI.getValueType(DL, T);
- return VT.isSimple() && VT.isInteger() &&
- VT.getSimpleVT().getSizeInBits() == 32;
+ if (!VT.isSimple() || !VT.isInteger() || VT.isVector())
+ return false;
+
+ unsigned VTSize = VT.getSimpleVT().getSizeInBits();
+ return VTSize == 8 || VTSize == 16 || VTSize == 32;
}
namespace {
@@ -53,9 +56,13 @@ struct FuncReturnHandler : public CallLo
assert(VA.isRegLoc() && "Value shouldn't be assigned to reg");
assert(VA.getLocReg() == PhysReg && "Assigning to the wrong reg?");
- assert(VA.getValVT().getSizeInBits() == 32 && "Unsupported value size");
+ assert(VA.getValVT().getSizeInBits() <= 32 && "Unsupported value size");
assert(VA.getLocVT().getSizeInBits() == 32 && "Unsupported location size");
+ assert(VA.getLocInfo() != CCValAssign::SExt &&
+ VA.getLocInfo() != CCValAssign::ZExt &&
+ "ABI extensions not supported yet");
+
MIRBuilder.buildCopy(PhysReg, ValVReg);
MIB.addUse(PhysReg, RegState::Implicit);
}
@@ -144,7 +151,7 @@ struct FormalArgHandler : public CallLow
assert(VA.isRegLoc() && "Value shouldn't be assigned to reg");
assert(VA.getLocReg() == PhysReg && "Assigning to the wrong reg?");
- assert(VA.getValVT().getSizeInBits() == 32 && "Unsupported value size");
+ assert(VA.getValVT().getSizeInBits() <= 32 && "Unsupported value size");
assert(VA.getLocVT().getSizeInBits() == 32 && "Unsupported location size");
MIRBuilder.getMBB().addLiveIn(PhysReg);
@@ -167,10 +174,18 @@ bool ARMCallLowering::lowerFormalArgumen
auto &TLI = *getTLI<ARMTargetLowering>();
auto &Args = F.getArgumentList();
- for (auto &Arg : Args)
+ unsigned ArgIdx = 0;
+ for (auto &Arg : Args) {
+ ArgIdx++;
if (!isSupportedType(DL, TLI, Arg.getType()))
return false;
+ // FIXME: This check as well as ArgIdx are going away as soon as we support
+ // loading values < 32 bits.
+ if (ArgIdx > 4 && Arg.getType()->getIntegerBitWidth() != 32)
+ return false;
+ }
+
CCAssignFn *AssignFn =
TLI.CCAssignFnForCall(F.getCallingConv(), F.isVarArg());
Modified: llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-irtranslator.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-irtranslator.ll?rev=290106&r1=290105&r2=290106&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-irtranslator.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-irtranslator.ll Mon Dec 19 08:08:02 2016
@@ -7,13 +7,39 @@ entry:
ret void
}
-define i32 @test_add(i32 %x, i32 %y) {
-; CHECK-LABEL: name: test_add
+define i8 @test_add_i8(i8 %x, i8 %y) {
+; CHECK-LABEL: name: test_add_i8
; CHECK: liveins: %r0, %r1
-; CHECK: [[VREGX:%[0-9]+]]{{.*}} = COPY %r0
-; CHECK: [[VREGY:%[0-9]+]]{{.*}} = COPY %r1
-; CHECK: [[SUM:%[0-9]+]]{{.*}} = G_ADD [[VREGX]], [[VREGY]]
-; CHECK: %r0 = COPY [[SUM]]
+; CHECK-DAG: [[VREGX:%[0-9]+]](s8) = COPY %r0
+; CHECK-DAG: [[VREGY:%[0-9]+]](s8) = COPY %r1
+; CHECK: [[SUM:%[0-9]+]](s8) = G_ADD [[VREGX]], [[VREGY]]
+; CHECK: %r0 = COPY [[SUM]](s8)
+; CHECK: BX_RET 14, _, implicit %r0
+entry:
+ %sum = add i8 %x, %y
+ ret i8 %sum
+}
+
+define i16 @test_add_i16(i16 %x, i16 %y) {
+; CHECK-LABEL: name: test_add_i16
+; CHECK: liveins: %r0, %r1
+; CHECK-DAG: [[VREGX:%[0-9]+]](s16) = COPY %r0
+; CHECK-DAG: [[VREGY:%[0-9]+]](s16) = COPY %r1
+; CHECK: [[SUM:%[0-9]+]](s16) = G_ADD [[VREGX]], [[VREGY]]
+; CHECK: %r0 = COPY [[SUM]](s16)
+; CHECK: BX_RET 14, _, implicit %r0
+entry:
+ %sum = add i16 %x, %y
+ ret i16 %sum
+}
+
+define i32 @test_add_i32(i32 %x, i32 %y) {
+; CHECK-LABEL: name: test_add_i32
+; CHECK: liveins: %r0, %r1
+; CHECK-DAG: [[VREGX:%[0-9]+]](s32) = COPY %r0
+; CHECK-DAG: [[VREGY:%[0-9]+]](s32) = COPY %r1
+; CHECK: [[SUM:%[0-9]+]](s32) = G_ADD [[VREGX]], [[VREGY]]
+; CHECK: %r0 = COPY [[SUM]](s32)
; CHECK: BX_RET 14, _, implicit %r0
entry:
%sum = add i32 %x, %y
Modified: llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-isel.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-isel.ll?rev=290106&r1=290105&r2=290106&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-isel.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-isel.ll Mon Dec 19 08:08:02 2016
@@ -7,8 +7,26 @@ entry:
ret void
}
-define i32 @test_add(i32 %x, i32 %y) {
-; CHECK-LABEL: test_add:
+define i8 @test_add_i8(i8 %x, i8 %y) {
+; CHECK-LABEL: test_add_i8:
+; CHECK: add r0, r0, r1
+; CHECK: bx lr
+entry:
+ %sum = add i8 %x, %y
+ ret i8 %sum
+}
+
+define i16 @test_add_i16(i16 %x, i16 %y) {
+; CHECK-LABEL: test_add_i16:
+; CHECK: add r0, r0, r1
+; CHECK: bx lr
+entry:
+ %sum = add i16 %x, %y
+ ret i16 %sum
+}
+
+define i32 @test_add_i32(i32 %x, i32 %y) {
+; CHECK-LABEL: test_add_i32:
; CHECK: add r0, r0, r1
; CHECK: bx lr
entry:
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