[llvm] r290105 - [ARM] GlobalISel: Allow i8 and i16 adds
Diana Picus via llvm-commits
llvm-commits at lists.llvm.org
Mon Dec 19 06:07:56 PST 2016
Author: rovka
Date: Mon Dec 19 08:07:56 2016
New Revision: 290105
URL: http://llvm.org/viewvc/llvm-project?rev=290105&view=rev
Log:
[ARM] GlobalISel: Allow i8 and i16 adds
Teach the instruction selector and legalizer that it's ok to have adds with 8 or
16-bit integers.
This is the second part of https://reviews.llvm.org/D27704
Modified:
llvm/trunk/lib/Target/ARM/ARMLegalizerInfo.cpp
llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-instruction-select.mir
llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-legalizer.mir
llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-regbankselect.mir
Modified: llvm/trunk/lib/Target/ARM/ARMLegalizerInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMLegalizerInfo.cpp?rev=290105&r1=290104&r2=290105&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMLegalizerInfo.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMLegalizerInfo.cpp Mon Dec 19 08:07:56 2016
@@ -25,7 +25,11 @@ using namespace llvm;
ARMLegalizerInfo::ARMLegalizerInfo() {
using namespace TargetOpcode;
+
const LLT p0 = LLT::pointer(0, 32);
+
+ const LLT s8 = LLT::scalar(8);
+ const LLT s16 = LLT::scalar(16);
const LLT s32 = LLT::scalar(32);
setAction({G_FRAME_INDEX, p0}, Legal);
@@ -33,7 +37,8 @@ ARMLegalizerInfo::ARMLegalizerInfo() {
setAction({G_LOAD, s32}, Legal);
setAction({G_LOAD, 1, p0}, Legal);
- setAction({G_ADD, s32}, Legal);
+ for (auto Ty : {s8, s16, s32})
+ setAction({G_ADD, Ty}, Legal);
computeTables();
}
Modified: llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-instruction-select.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-instruction-select.mir?rev=290105&r1=290104&r2=290105&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-instruction-select.mir (original)
+++ llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-instruction-select.mir Mon Dec 19 08:07:56 2016
@@ -27,8 +27,14 @@ body: |
%0(s8) = COPY %r0
; CHECK: [[VREGX:%[0-9]+]] = COPY %r0
- %r0 = COPY %0(s8)
- ; CHECK: %r0 = COPY [[VREGX]]
+ %1(s8) = COPY %r1
+ ; CHECK: [[VREGY:%[0-9]+]] = COPY %r1
+
+ %2(s8) = G_ADD %0, %1
+ ; CHECK: [[VREGSUM:%[0-9]+]] = ADDrr [[VREGX]], [[VREGY]], 14, _, _
+
+ %r0 = COPY %2(s8)
+ ; CHECK: %r0 = COPY [[VREGSUM]]
BX_RET 14, _, implicit %r0
; CHECK: BX_RET 14, _, implicit %r0
@@ -54,8 +60,14 @@ body: |
%0(s16) = COPY %r0
; CHECK: [[VREGX:%[0-9]+]] = COPY %r0
- %r0 = COPY %0(s16)
- ; CHECK: %r0 = COPY [[VREGX]]
+ %1(s16) = COPY %r1
+ ; CHECK: [[VREGY:%[0-9]+]] = COPY %r1
+
+ %2(s16) = G_ADD %0, %1
+ ; CHECK: [[VREGSUM:%[0-9]+]] = ADDrr [[VREGX]], [[VREGY]], 14, _, _
+
+ %r0 = COPY %2(s16)
+ ; CHECK: %r0 = COPY [[VREGSUM]]
BX_RET 14, _, implicit %r0
; CHECK: BX_RET 14, _, implicit %r0
Modified: llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-legalizer.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-legalizer.mir?rev=290105&r1=290104&r2=290105&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-legalizer.mir (original)
+++ llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-legalizer.mir Mon Dec 19 08:07:56 2016
@@ -1,9 +1,61 @@
# RUN: llc -mtriple arm-- -global-isel -run-pass=legalizer %s -o - | FileCheck %s
--- |
+ define void @test_add_s8() { ret void }
+ define void @test_add_s16() { ret void }
define void @test_add_s32() { ret void }
+
define void @test_load_from_stack() { ret void }
...
---
+name: test_add_s8
+# CHECK-LABEL: name: test_add_s8
+legalized: false
+# CHECK: legalized: true
+regBankSelected: false
+selected: false
+tracksRegLiveness: true
+registers:
+ - { id: 0, class: _ }
+ - { id: 1, class: _ }
+ - { id: 2, class: _ }
+body: |
+ bb.0:
+ liveins: %r0, %r1
+
+ %0(s8) = COPY %r0
+ %1(s8) = COPY %r1
+ %2(s8) = G_ADD %0, %1
+ ; G_ADD with s8 is legal, so we should find it unchanged in the output
+ ; CHECK: {{%[0-9]+}}(s8) = G_ADD {{%[0-9]+, %[0-9]+}}
+ %r0 = COPY %2(s8)
+ BX_RET 14, _, implicit %r0
+...
+---
+name: test_add_s16
+# CHECK-LABEL: name: test_add_s16
+legalized: false
+# CHECK: legalized: true
+regBankSelected: false
+selected: false
+tracksRegLiveness: true
+registers:
+ - { id: 0, class: _ }
+ - { id: 1, class: _ }
+ - { id: 2, class: _ }
+body: |
+ bb.0:
+ liveins: %r0, %r1
+
+ %0(s16) = COPY %r0
+ %1(s16) = COPY %r1
+ %2(s16) = G_ADD %0, %1
+ ; G_ADD with s16 is legal, so we should find it unchanged in the output
+ ; CHECK: {{%[0-9]+}}(s16) = G_ADD {{%[0-9]+, %[0-9]+}}
+ %r0 = COPY %2(s16)
+ BX_RET 14, _, implicit %r0
+
+...
+---
name: test_add_s32
# CHECK-LABEL: name: test_add_s32
legalized: false
@@ -56,5 +108,4 @@ body: |
%0(p0) = G_FRAME_INDEX %fixed-stack.2
%1(s32) = G_LOAD %0(p0)
BX_RET 14, _
-
...
Modified: llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-regbankselect.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-regbankselect.mir?rev=290105&r1=290104&r2=290105&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-regbankselect.mir (original)
+++ llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-regbankselect.mir Mon Dec 19 08:07:56 2016
@@ -1,6 +1,8 @@
# RUN: llc -mtriple arm-- -global-isel -run-pass=regbankselect %s -o - | FileCheck %s
--- |
define void @test_add_s32() { ret void }
+ define void @test_add_s16() { ret void }
+ define void @test_add_s8() { ret void }
...
---
name: test_add_s32
@@ -28,3 +30,55 @@ body: |
BX_RET 14, _, implicit %r0
...
+---
+name: test_add_s16
+# CHECK-LABEL: name: test_add_s16
+legalized: true
+regBankSelected: false
+selected: false
+# CHECK: registers:
+# CHECK: - { id: 0, class: gprb }
+# CHECK: - { id: 1, class: gprb }
+# CHECK: - { id: 2, class: gprb }
+
+registers:
+ - { id: 0, class: _ }
+ - { id: 1, class: _ }
+ - { id: 2, class: _ }
+body: |
+ bb.0:
+ liveins: %r0, %r1
+
+ %0(s16) = COPY %r0
+ %1(s16) = COPY %r1
+ %2(s16) = G_ADD %0, %1
+ %r0 = COPY %2(s16)
+ BX_RET 14, _, implicit %r0
+
+...
+---
+name: test_add_s8
+# CHECK-LABEL: name: test_add_s8
+legalized: true
+regBankSelected: false
+selected: false
+# CHECK: registers:
+# CHECK: - { id: 0, class: gprb }
+# CHECK: - { id: 1, class: gprb }
+# CHECK: - { id: 2, class: gprb }
+
+registers:
+ - { id: 0, class: _ }
+ - { id: 1, class: _ }
+ - { id: 2, class: _ }
+body: |
+ bb.0:
+ liveins: %r0, %r1
+
+ %0(s8) = COPY %r0
+ %1(s8) = COPY %r1
+ %2(s8) = G_ADD %0, %1
+ %r0 = COPY %2(s8)
+ BX_RET 14, _, implicit %r0
+
+...
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