[PATCH] D27694: [ARM] Add ARMISD::VLD1DUP to match vld1_dup more consistently

Eli Friedman via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Mon Dec 12 18:02:04 PST 2016


efriedma created this revision.
efriedma added reviewers: t.p.northover, jmolloy.
efriedma added subscribers: llvm-commits, grosbach, bob.wilson.
efriedma set the repository for this revision to rL LLVM.
Herald added subscribers: rengolin, aemerson.

Currently, there are substantial problems forming vld1_dup even if the
VDUP survives legalization.  The lack of an actual node
leads to terrible results: not only can we not form post-increment vld1_dup
instructions, but we form scalar pre-increment and post-increment
loads which force the loaded value into a GPR.  This patch fixes that
by combining the vdup+load into an ARMISD node before DAGCombine
messes it up.

Also includes a crash fix for vld2_dup (see testcase @vld2dupi8_postinc_variable).

Not sure who to ask to review this...


Repository:
  rL LLVM

https://reviews.llvm.org/D27694

Files:
  lib/Target/ARM/ARMISelDAGToDAG.cpp
  lib/Target/ARM/ARMISelLowering.cpp
  lib/Target/ARM/ARMISelLowering.h
  test/CodeGen/ARM/vlddup.ll
  test/CodeGen/ARM/vmul.ll

-------------- next part --------------
A non-text attachment was scrubbed...
Name: D27694.81168.patch
Type: text/x-patch
Size: 19865 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20161213/acaeb079/attachment.bin>


More information about the llvm-commits mailing list