[PATCH] D27677: [AArch64] Guard Misaligned 128-bit store penalty by subtarget feature

[Evandro Menezes via Phabricator via llvm-commits]

evandro added a comment.

This feature is rather a subset of `FeatureAvoidQuadLdStPairs`, used in `AArch64InstrInfo::isCandidateToMergeOrPair()`, which effectively avoids any 128 load or store, aligned or misaligned.

I actually wonder if, for uniformity's sake, `FeatureAvoidQuadLdStPairs` should be renamed `FeatureSlow128LoadStore`.  Thoughts?


https://reviews.llvm.org/D27677