[PATCH] D27677: [AArch64] Guard Misaligned 128-bit store penalty by subtarget feature

[Matthew Simpson via Phabricator via llvm-commits]

mssimpso retitled this revision from "[AArch64] Add feature for disabling unaligned quadword store penalty" to "[AArch64] Guard Misaligned 128-bit store penalty by subtarget feature".
mssimpso updated the summary for this revision.
mssimpso added reviewers: jmolloy, sebpop.
mssimpso updated this revision to Diff 81123.
mssimpso marked an inline comment as done.
mssimpso added a comment.

Addressed Matthias's comments. Thanks!

- We now use the existing FeatureSlowMisaligned128Store instead of adding a new feature.
- I added James and Sebastian to the review for opinions about non-Cyclone CPUs.


https://reviews.llvm.org/D27677

Files:
  lib/Target/AArch64/AArch64TargetTransformInfo.cpp
  test/Analysis/CostModel/AArch64/store.ll


Index: test/Analysis/CostModel/AArch64/store.ll
===================================================================
--- test/Analysis/CostModel/AArch64/store.ll
+++ test/Analysis/CostModel/AArch64/store.ll
@@ -1,10 +1,16 @@
-; RUN: opt < %s  -cost-model -analyze -mtriple=arm64-apple-ios -mcpu=cyclone | FileCheck %s
+; RUN: opt < %s  -cost-model -analyze -mtriple=arm64-apple-ios -mattr=slow-misaligned-128store | FileCheck %s --check-prefix=SLOW_MISALIGNED_128_STORE
+; RUN: opt < %s  -cost-model -analyze -mtriple=arm64-apple-ios | FileCheck %s
+
 target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:32:64-v128:32:128-a0:0:32-n32-S32"
 ; CHECK-LABEL: store
+; SLOW_MISALIGNED_128_STORE-LABEL: store
 define void @store() {
-    ; Stores of <2 x i64> should be expensive because we don't split them and
-    ; and unaligned 16b stores have bad performance.
-    ; CHECK: cost of 12 {{.*}} store
+    ; If FeatureSlowMisaligned128Store is set, we penalize <2 x i64> stores.
+    ; Such stores are expensive because we assume they will not be split and
+    ; that 16b stores have bad performance.
+    ;
+    ; SLOW_MISALIGNED_128_STORE: cost of 12 {{.*}} store
+    ; CHECK: cost of 1 {{.*}} store
     store <2 x i64> undef, <2 x i64> * undef
 
     ; We scalarize the loads/stores because there is no vector register name for
Index: lib/Target/AArch64/AArch64TargetTransformInfo.cpp
===================================================================
--- lib/Target/AArch64/AArch64TargetTransformInfo.cpp
+++ lib/Target/AArch64/AArch64TargetTransformInfo.cpp
@@ -467,7 +467,8 @@
                                     unsigned Alignment, unsigned AddressSpace) {
   std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, Src);
 
-  if (Opcode == Instruction::Store && Src->isVectorTy() && Alignment != 16 &&
+  if (ST->isMisaligned128StoreSlow() && Opcode == Instruction::Store &&
+      Src->isVectorTy() && Alignment != 16 &&
       Src->getVectorElementType()->isIntegerTy(64)) {
     // Unaligned stores are extremely inefficient. We don't split
     // unaligned v2i64 stores because the negative impact that has shown in


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