[PATCH] D27293: [WIP] Cleanup SplitCSR implementation

[Philip Reames via Phabricator via llvm-commits]

reames created this revision.
reames added a reviewer: MatzeB.
reames added a subscriber: llvm-commits.
Herald added subscribers: amehsan, nemanjai, mcrosier, aemerson.

Very much WIP, posting for discussion, will cleanup based on input.

Key question: Is minimal phys reg the right helper routine to be using here?  The ARM backend change makes me wonder.  It does match what the x86 backend uses for non-GPR spills along the "normal" spill insertion path.

SplitCSR is an off by default mode which let's the register allocator handle spilling CSRs as normal vregs.  This really should be the default, but for historical reasons isn't.

This change tries to remove the target specific differences from the copied implementations.  Once this is in, a simple NFC change will sink a shared implementation into the base class and delete all of the overrides.


https://reviews.llvm.org/D27293

Files:
  lib/Target/AArch64/AArch64ISelLowering.cpp
  lib/Target/ARM/ARMBaseRegisterInfo.cpp
  lib/Target/ARM/ARMISelLowering.cpp
  lib/Target/ARM/Thumb2InstrInfo.cpp
  lib/Target/PowerPC/PPCISelLowering.cpp
  lib/Target/X86/X86ISelLowering.cpp
  lib/Target/X86/X86ISelLowering.h

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