[PATCH] D25914: Redo store splitting in CodeGenPrepare

[Wei Mi via llvm-commits]

wmi added inline comments.


================
Comment at: lib/CodeGen/CodeGenPrepare.cpp:5218-5233
+  if (!OR || OR->getOpcode() != Instruction::Or ||
+      OR->getParent() != SI.getParent())
+    return false;
+
+  // Match SHL operand and get Lower and Higher parts of Val.
+  Value *Op1 = OR->getOperand(0);
+  Value *Op2 = OR->getOperand(1);
----------------
chandlerc wrote:
> Have you looked at doing this with the IR pattern match library? (I should have mentioned this earlier, sorry.) Check out the PatternMatch.h header.
> 
> Something like:
> 
>   unsigned HalfValBitSize = ...;
>   Value *Lo, *Hi;
>   if (match(SI.getValueOperand(),
>             m_c_Or(m_OneUse(m_Shl(m_ZExt(m_Value(Hi)), m_SpecificInt(HalfValBitSize))),
>                    m_ZExt(m_Value(Lo)))))
> 
> I forget the exact syntax for matching zero extends, but I think you can capture most of this in a very small number of lines of code.
I rewrite it using pattern match library. It is really awesome. The code becomes much simpler. 


================
Comment at: lib/CodeGen/CodeGenPrepare.cpp:5219
+  if (!OR || OR->getOpcode() != Instruction::Or ||
+      OR->getParent() != SI.getParent())
+    return false;
----------------
chandlerc wrote:
> Why not go ahead and handle cases within a BB?
I forgot the exact reason I added it.  I remove the restriction and add a testcase for it.


Repository:
  rL LLVM

https://reviews.llvm.org/D25914