[PATCH] D26648: Clarify semantic of reserved registers.

[Quentin Colombet via llvm-commits]

Hi,

> On Nov 15, 2016, at 11:13 AM, Matthias Braun <matze at braunis.de> wrote:
> 
> MatzeB added a comment.
> 
> In https://reviews.llvm.org/D26648#595589, @sdardis wrote:
> 
>> @MatzeB Yes, we could rework the floating point register set definitions and instruction definitions to use difference register classes depending the floating point ABI used. Unfortunately this requires six register classes in that case, three for the no odd single precision case and 3 more for the case where odd single precisions are available. Those register classes would eliminate the need to reserve the odd registers for no-oddsp.
>> 
>> That's a non-trivial change which will take some time as other plumbing may need to be fixed/changed.
>> 
>> Some background:
>> The difficulty/delay arises in that MIPS has several different FPU configurations: 32bit FPUs supporting 64bit operations using a pair of single precision registers, and full 64bit FPUs. We have two floating pointing ABIs: nooddsp where the odd single precision registers are not to be used at all, and oddsp where all single precision registers can be used.
> 
> 
> Hi,
> 
> after working on this for a while I think the proposed rules here should rather be guidelines.

Hmm, I found this concerning. I don’t see how we can guarantee that regalloc will be correct if people don’t follow the guidelines and thus, if we allow to not follow the guidelines, what sort of support do we enforce other than “if you’re not following the guidelines, your code may be broken”?

> They are the right thing in many situations, but not all. I reworked the commit in a way that backends can call assertAllSuperRegsMarked() at their own discretion.
> 
> 
> Repository:
>  rL LLVM
> 
> https://reviews.llvm.org/D26648
> 
> 
>