[PATCH] D26605: [DAGCombiner] Fix infinite loop in vector mul/shl combining

[Simon Pilgrim via llvm-commits]

RKSimon added inline comments.


================
Comment at: lib/CodeGen/SelectionDAG/DAGCombiner.cpp:2163
     SDValue C3 = DAG.getNode(ISD::SHL, SDLoc(N), VT, N1, N0.getOperand(1));
-    AddToWorklist(C3.getNode());
+    assert(isConstantOrConstantVector(C3) && "Failed to constant fold");
     return DAG.getNode(ISD::MUL, SDLoc(N), VT, N0.getOperand(0), C3);
----------------
I'm worried that maybe instead of asserting for a constant value we should just use an if() - there still might end up being odd cases where the constant fold still fails for some reason. Same for the other case below. What do you think?


================
Comment at: lib/CodeGen/SelectionDAG/SelectionDAG.cpp:3476
     // Avoid BUILD_VECTOR nodes that perform implicit truncation.
     // FIXME: This is valid and could be handled by truncating the APInts.
     if (V1->getValueType(0) != SVT || V2->getValueType(0) != SVT)
----------------
These aren't APInt any more:

```
// FIXME: This is valid and could be handled by truncation.
```


Repository:
  rL LLVM

https://reviews.llvm.org/D26605